AMD CEO Lisa Su arrived in Taiwan on May 20, 2026, on a private jet and largely followed the same itinerary as her April 2025 visit, including a meeting with TSMC, a technology forum and dinner with Taiwan supply chain partners, and an about one-hour summit forum. This time, AMD also made the rare announcement that it will invest more than US$10 billion in Taiwan's industrial ecosystem to accelerate AI infrastructure buildout.
The company said the latest cooperation progress spans Taiwan's AI supply chain, led by TSMC, ASE, Powertech, and multiple substrate makers. AMD also announced that its Venice EPYC processors using TSMC's 2nm process have entered mass production.
AMD also highlighted development of the Elevated Fanout Bridge (EFB) ecosystem, saying it is working with ASE, SPIL, and others to jointly develop and validate next-generation wafer-based 2.5D bridge interconnect technology. That effort is seen as a push to back an alternative advanced packaging path beyond TSMC's CoWoS.
Su reoprtedly planned the Taiwan trip well in advance and personally hosted "AMD AI DevDay 2026" in Shanghai before arriving. Ahead of her May 22 speech at the CommonWealth Economic Forum, she also met Taiwan supply chain partners and customers for technical exchanges and dinner the day before.
The invitation list covered upstream and downstream partners across semiconductors, AI servers, PCs, boards, and memory, including ASE, Nan Ya PCB, Wistron, Asus, Gigabyte, ASRock, ASMedia, and Phison, among dozens of other major companies.
Why AMD skipped Computex
Supply chain sources said Su did not attend Computex, and AMD had no major public keynote or event there, because the show is crowded with presentations and activities from companies such as Nvidia, Intel, and Qualcomm, making the promotional overlap less effective. By arriving in Taiwan early, AMD also gave partners more breathing room in scheduling, while its public remarks on AI development drew broader attention.
AMD has also been moving fast elsewhere. In March, it signed a memorandum of understanding with Samsung Electronics to expand strategic cooperation on next-generation AI memory and computing technologies and explore foundry collaboration opportunities. Supply chain sources said AMD is broadening its ties with Samsung because it urgently needs more memory capacity.
Back in the AI server arena, Taiwan's supply chain continues to hold an edge in end-to-end integration and technical innovation. Beyond the server-related ecosystem, Taiwan also leads in foundry, packaging, and testing, while companies such as WinWay, KYEC, and iST have worked with AMD for years on testing, verification, and analysis.
That is why AMD's annual dinner with Taiwan's large supply chain network, where it explains its latest technologies and outlook, underscores Taiwan's strategic importance.
US$10B-plus investment targets advanced packaging
AMD said it will invest more than US$10 billion in Taiwan's industrial ecosystem to deepen strategic partnerships and expand advanced packaging capacity for AI infrastructure. It also said Venice, its EPYC processor using TSMC's 2nm process, has entered mass production, underscoring the closeness of the two companies' collaboration.
Supply chain sources said AMD wants to reinforce ties with TSMC, ASE, and other Taiwan-based partners through the move.
AMD said it is working closely with strategic partners in Taiwan and globally to advance chip, packaging and manufacturing technologies that deliver higher performance, better efficiency and faster AI system deployment. The newly announced investment plan shows how strategic partnerships are driving the chip, packaging, and manufacturing innovation needed for next-generation AI infrastructure.
In the EFB ecosystem specifically, AMD is working with ASE, SPIL, and others to co-develop and validate next-generation wafer-based 2.5D bridge interconnect technology.
AMD said the EFB architecture can significantly increase interconnect bandwidth and improve power efficiency, supporting the Venice CPU. Its collaboration with Powertech is validating the industry's first 2.5D panel-level EFB interconnect technology, which supports large-scale, high-bandwidth interconnects and helps customers deploy more efficient AI systems with better overall economics.
Substrate suppliers Unimicron, Nan Ya PCB, and Kinsus Tech, as well as AIC in rack-level and compute tray design, are also on the collaboration list.
Supply chain sources said AMD's specific reference to the EFB ecosystem suggests that TSMC's CoWoS capacity remains tight and that AMD has limited access, prompting the company to actively seek advanced packaging technologies beyond CoWoS.
AMD also said it will work with partners to use these technologies to support deployment of the Helios rack-scale platform in second half 2026. ODM partners including Sanmina, Wiwynn, Wistron, and Inventec are helping build Helios-based systems.
Meanwhile, AMD said CPUs are playing an increasingly critical role as AI applications expand from training and inference to more complex agentic workloads. Venice has entered mass production, and AMD plans to start mass production at TSMC's Arizona fab in the future.
Venice production in Taiwan, along with the planned capacity expansion at TSMC's Arizona fab, also reflects AMD's continued effort to strengthen a geographically diversified advanced manufacturing footprint. AMD also plans to extend TSMC's 2nm process technology to Verano, its data center CPU roadmap.
Verano is designed for cloud and AI computing workloads and is expected to build on the EPYC platform with advanced memory innovations including LPDDR, aiming to deliver the CPU performance, bandwidth and energy efficiency required for increasingly power-constrained workloads and applications.
AMD's collaboration with TSMC covers key technologies needed to expand modern data center computing, from TSMC's 2nm process for next-generation CPUs to advanced packaging technologies including TSMC SoIC-X and CoWoS-L.
Article translated by Charlene Chen and edited by Joseph Chen