Improved testing is important, but cost is key. Healy cited Qualcomm as finding no problems in 61% of field returns; he attributed this to insufficient testing.
Because of current organization, DFT may be cut to save cost and speed time to market, but this may be a false saving. Small increases in design time can improve time to market and reduce cost of tests. With wafer-level testing at full speed (with BIST), yield at final test improves. This also means less testers as test times are faster.
DFT is a value play, not a cost play.
Samsung HKMG DDR5
Samsung Electronics has expanded its DDR5 DRAM memory portfolio with a 512GB DDR5 module...
Photo: Company
Nvidia GeForce RTX 30 series GPUs
Nvidia's GeForce RTX 30 series GPUs are powered by the company's Ampere architecture. The...
Photo: Company
Apple HomePod mini
Apple's HomePod mini is the newest addition to the HomePod family. At just 3.3 inches tall,...
Photo: Company
Apple 13-inch MacBook Pro with Magic Keyboard
Apple has updated the 13-inch MacBook Pro with the new Magic Keyboard for an improved typing...
Photo: Company
Apple iPad Pros
Apple's new iPad Pros comes with the latest A12Z Bionic chip, an ultra-wide camera, studio-quality...
Photo: Company
As Microsoft transitions from a software giant to a cloud leader, with its cloud business now accounting...
Essential technology and geopolitical news recap, GeoWatch, focuses on the tech supply chain, providing effortless insights.
CSP in-house development of ASIC accelerators
Google TPUs will see a share of over 70% in the in-house developed cloud ASIC accelerator market in 2024; an all-optical network...
AI chip market outlook 2023-2028: Insights from demand and supply perspectives
The growing demand for AI computational power is accelerating advancements in hardware and chip technology, necessitating innovation...
Automotive CIS tech development, 2024
The popularization of autonomous driving is boosting demand for automotive CIS with LFM and HDR being mainstream development...