SK hynix Inc. (or "the company", www.skhynix.com) announced today that it has shipped samples of HBM4E, a next-generation DRAM for AI, to major customers."The company was able to deliver samples of the 12-stack HBM4E on schedule thanks to its advanced HBM development and production expertise for HBM," said SK hynix, adding that "We will work closely with partners for mass production in a timely manner." The 12-layer HBM4E shows improvements in both performance and power efficiency. The product features a maximum data processing speed of 16Gbps per pin and power efficiency that is up more than 20 percent from previous models. These enhancements improve data processing capabilities for AI training and inference.The HBM4E reduces data transfer latency through its latest interface and design optimization while maintaining stable operation in high-bandwidth environments. This enables customers to increase efficiency in processing data for AI datacenters and large-scale computing systems. SK hynix utilizes Advanced MR-MUF technology for HBM4E products to achieve a 48GB capacity in a 12-layer stack while ensuring structural stability. In particular, the company has also improved heat resistance by 17 percent, compared to the preceding HBM4, enabling stable operation of memory chips in high-performance computing environments.SK hynix has successfully supplied optimized memory solutions to customers based on its expertise in the mass production and supply of HBM3, HBM3E, and HBM4. Leveraging its market-proven product reliability and supply capabilities, the company will support the development of next-generation infrastructure while helping address AI system bottlenecks. "SK hynix has laid the foundation to strengthen its AI leadership with HBM4E based on its market-leading technological capabilities and manufacturing expertise," said Ahn Hyun, President and Chief Development Officer, adding, "Through close collaboration with our partners, we will deliver the value needed in the market while reinforcing our technology leadership as a full-stack AI memory creator."Credit: SK hynix

Advanced Chip and Circuit Materials today announces the commercial availability of Celeritas HM50 and Celeritas HM001, which eliminate the root causes of warpage, package bow, solder fatigue, and high-frequency signal loss in large-format AI accelerators and advanced chip packaging architectures. Celeritas HM50 is a negative CTE (-8 PPM/°C) material and Celeritas HM001 is a near-zero CTE material. Used together in a single stackup, they bring board CTE below 10 ppm/°C while simultaneously delivering Tier 9 electrical performance.Every hyperscaler building AI infrastructure is confronting the same pair of converging constraints. As AI accelerators scale beyond reticle limits, thermomechanical mismatch between silicon (2–4 ppm/°C) and standard PCB materials (~18 ppm/°C) produces catastrophic reflow warpage, package bow, and solder joint fatigue. Simultaneously, the explosive growth in data rates, driven by HBM, UCIe, and chip-to-chip interconnect operating at 100+ Gbps, is pushing signal integrity requirements beyond what standard PCB dielectrics can support. The industry has been searching for two separate solutions to two separate problems. ACCM has built one material family that addresses both.The industry's leading proposed fix of solid glass substrates remains positive in CTE and does not address the electrical side at all. ACCM today announced Celeritas HM50 and Celeritas HM001, which together solve both problems simultaneously. Programs can start today.Celeritas HM50 FEA – Standard PCB at 18 ppm/°C (left) vs. PCB with HM50 at 10 ppm/°C (right). FR4 PCB baseline fails JEDEC qualification, while the PCB with HM50 shows >100× improvement. Warpage and Package Bow are reduced by 64%, and 81%, respectively. Combined HM50+HM001 stackups achieve even lower effective CTE.Keshav Amla, COO of Advanced Chip & Circuit Materials, said,"Rather than incrementally tuning stackups, we are applying a breakthrough materials innovation to remove a fundamental limitation that has constrained system scaling. HM50, with its negative CTE of -8 PPM/°C, drives the effective CTE of the board down. Even with heavy copper designs, you could tune a board down to 12, 10, 8 PPM/°C or lower. And where next-generation data rates demand extreme loss performance, HM001 replaces those layers with a Tier 9 loss material that has a near-zero CTE. Together, they give designers headroom they simply have not had before."The HM Class of materials matches each layer type in an AI accelerator stackup with a material purpose-built for it: HM50 for the power planes, HM001 for the signal layers. As AI accelerators grow in scale, the industry has long struggled with two separate problems — boards warping under thermal stress, and signal loss at extreme data rates. ACCM's Celeritas material family tackles both within a single solution. Celeritas HM50 counteracts the thermal expansion mismatch that causes warpage and solder joint failures, enabling designs that previously failed industry qualification to now meet it with significant margin. Celeritas HM001 addresses the signal integrity side, supporting the data rate demands of next-generation AI interconnects while also contributing to thermal stability. Together, the two materials give chip and board designers headroom that standard PCB materials have not been able to provide. For more details, please visit here.Credit: Advanced Chip and Circuit Materials

As artificial intelligence (AI) becomes increasingly sophisticated, the demand for higher processing power, speed and efficiency in computing has surged. Next-generation technologies, from enterprise data centers (EDCs) and AI PCs to the Internet of Things (IoT) and 6G communications, require unprecedented bandwidth. However, as data rates climb, ensuring signal integrity during semiconductor testing becomes exponentially more difficult. Even slight impedance mismatches or signal degradation can trigger false failures, compromise yields and delay critical product launches.To address these fundamental industry challenges, Smiths Interconnect, a Molex company, has introduced the DaVinci Gen V test socket. Built upon a patented mechanical foundation, this fifth-generation coaxial test socket provides an out-of-the-box solution engineered to overcome impedance tuning and signal degradation hurdles. The product rigorously tests semiconductor chips during manufacturing to ensure they deliver ultra-reliable, lab-grade accuracy in high-volume production environments.Core Mechanical InnovationsThe performance of the DaVinci Gen V is rooted in its core mechanical innovations. A new signal cavity design allows for superior impedance control, establishing a cleaner and more reliable signal path. This is achieved through enhanced conductor-to-ground concentricity, which minimizes signal degradation and surpasses all previous DaVinci series models. The socket utilizes spring probe technology featuring a homogeneous alloy plated with gold to ensure better grounding. These precision probes deliver a consistent, stable contact resistance averaging as low as 33 milliohms and boast a long contact life that has been tested up to 500,000 insertions.Electrical Performance and Signal IntegrityThe electrical performance of the DaVinci Gen V sets a new benchmark for semiconductor validation. Designed to overcome the physical challenge of scaling impedance for next-generation chips, the socket supports staggering digital speeds. It enables unprecedented signaling speeds of up to 224Gbps PAM-4 for AI accelerators and speeds beyond 100 GHz for future 6G networks.In terms of RF characteristics, the DaVinci Gen V delivers a bandwidth greater than 84 GHz at a -1 dB insertion loss. The architecture utilizes a short signal path with a 4.90mm test height and the impedance can be precisely tuned to match the system or be defined as needed.Operational and Manufacturing AdvantagesBeyond raw speed, the DaVinci Gen V is engineered for streamlined, scalable manufacturing. The socket accommodates high co-planarity and features a tri-temp design capable of operating in extreme environments ranging from -55°C to 150°C. This robust mechanical performance ensures that the exact same socket can be utilized across manual test, bench test and high-volume manufacturing production test stages, guaranteeing consistency.Recognizing that modern integrated circuits are rapidly growing in complexity and size, the DaVinci Gen V was designed to easily accommodate an increase in next-generation ASIC (application specific integrated circuit) sizes. Despite this scalability, it maintains full compatibility with existing test hardware and PCB socket footprints. This backward compatibility allows manufacturers to transition effortlessly, saving costs, reducing development cycles and significantly accelerating time-to-market. The socket is also highly serviceable in the field, permitting the replacement of a single probe or the full array, and can be cleaned while the system is running using a cleaning surrogate.Target End Markets and Proven ApplicationsThe broad capabilities of the DaVinci Gen V make it well suited for a wide range of advanced semiconductor applications. Target end markets include data center processors such as CPUs and GPUs, AI accelerators and ASICs, high-performance computing and tensor processors, network switches and FPGA-based 224G SerDes devices, as well as autonomous vehicle and ADAS chips. As demand for higher bandwidth and faster data processing continues to grow, these applications require increasingly stringent testing accuracy and signal integrity performance.Its effectiveness in high-stakes, high-volume environments is already proven. Since the product's launch, Smiths Interconnect has secured a key program with a leading technology company to support their advanced AI GPU accelerator chips.Building on this initial success, the company was subsequently awarded a next-generation accelerator chip program with the same partner. This continued partnership  underscores the superior performance, innovation, and reliability of Smiths Interconnect’s test socket technology.The DaVinci Gen V test socket redefines high-speed semiconductor testing by combining advanced, patented insulated metal technology with precision impedance tuning. It effectively eliminates measurement errors while guaranteeing lab-grade accuracy and repeatability in robust production settings. By enabling the reliable validation of high-bandwidth devices, the DaVinci Gen V ensures that manufacturers are fully equipped to meet the performance demands and future-readiness requirements of tomorrow's most complex integrated circuits. Contact Smiths Interconnect  to learn more.DaVinci Gen V supports AI accelerators, GPUs and data center processors. Credit: Smiths Interconnect