As AI, high-performance computing (HPC), and advanced packaging continue to move toward higher levels of power integration, chip power consumption is rising rapidly. Thermal management has therefore become a critical factor affecting performance, reliability, and system design. World Diamond Technology is advancing its large-area diamond growth technology and accelerating the mass production of 300 mm diamond wafers to address the thermal management needs of AI chips and advanced packaging. Five Key Priorities for Mass ProductionThe 300 mm wafer is currently the mainstream format in advanced semiconductor manufacturing. Scaling diamond materials from conventional smaller sizes to 300 mm involves far more than simply increasing the surface area. It also presents multiple technical challenges related to large-area material processing, uniformity, thickness, flatness, internal stress, and surface quality. World Diamond Technology has continued to advance its large-area diamond growth technology and has secured a Taiwan patent (TW Patent: I840846). Its mass-production strategy focuses on five key priorities:(1)Optimizing the diamond growth process through proprietary WDCVDTM diamond growth technology to ensure consistency across large-area wafers.(2)Precisely controlling wafer thickness and uniformity to meet the stringent requirements of advanced packaging thermal management modules.(3)Strengthening flatness and internal stress management to improve yield and reliability.(4)Optimizing surface quality and process consistency to minimize defects.(5)Continuously improving production yield and capacity while establishing a stable supply chain to support customers' volume-production requirements. By advancing toward the 300 mm format, World Diamond Technology aims to increase the potential for integrating diamond materials with existing semiconductor processes and wafer-level application platforms, enabling diamond to progress from a specialty material toward large-scale adoption across the semiconductor industry. Advantages of Diamond MaterialsDiamond offers multiple advantages as a thermal management material. Its thermal conductivity can exceed 1,500 W/(m·K), significantly outperforming conventional heat-dissipation materials. Diamond also features an extremely low coefficient of thermal expansion, helping substantially improve device reliability.In addition, diamond delivers exceptional hardness, wear resistance, high-temperature durability, and chemical stability. These properties enable it to resist corrosion, operate reliably in high-temperature environments, extend product service life, and reduce the total cost of ownership. Targeting AI Chips and Advanced Packaging ApplicationsWorld Diamond Technology's  300 mm diamond wafers will focus on high-power, high-heat-flux semiconductor applications, including:(1)AI GPUs and HPC systems(2)Data centers and servers(3)2.5D and 3D advanced packaging(4)High-power laser devices(5)Automotive electronics and power modules As advanced packaging architectures become increasingly complex, thermal management is evolving from conventional system-level cooling toward package-level, device-level, and even wafer-level solutions. Consequently, the importance of high-thermal-conductivity materials will continue to grow. Diamond Technology Powering a High-Efficiency FutureWorld Diamond Technology stated that the 300 mm diamond wafer represents an important milestone in the company's efforts to industrialize large-area diamond materials. In the next phase, the company will continue to focus on process stabilization, yield improvement, specification standardization, customer validation, and the establishment of volume-production capabilities. It will also actively pursue collaboration with semiconductor manufacturers, advanced packaging companies, thermal module suppliers, and end-system providers. To meet the rapidly growing thermal management demands of the AI era, World Diamond Technology will continue to advance diamond materials from material development to practical semiconductor applications. The company is accelerating the establishment of a comprehensive technology portfolio spanning diamond wafers, diamond lids, diamond heat spreaders, and system-level thermal management solutions, positioning itself to capture opportunities in the next generation of high-power chips and advanced packaging. Discover the latest developments in diamond wafer technology at SEMICON Taiwan 2026. We cordially invite you to visit World Diamond Technology at Booth S7546 on the 4th floor of Taipei Nangang Exhibition Center, Hall 2.

DAS Environmental Expert GmbH today announced the launch of ALCEA, a new secondary abatement solution for nitrogen oxide (NOx) emissions in semiconductor manufacturing. Installed downstream of NOx-generating waste gas treatment units, ALCEA can reduce NOx by up to 95 percent while its catalyst stage is integrated directly into the exhaust duct, minimizing additional floor space in the subfab. DAS Environmental Experts will present the new system at SEMICON Taiwan 2026 from September 2 to 4 at TaiNEX 1 and 2 in Taipei (Booth J2 | 346).New plasma-enhanced catalytic secondary abatement solution integrates into exhaust ducts to minimize subfab floor space and energy demand In semiconductor fabs, additional emission-control capacity competes for limited and costly subfab space. At the same time, manufacturers are seeking to reduce utility demand, maintenance requirements, and operational interruptions. ALCEA addresses these constraints through a highly integrated architecture: the catalyst unit is fitted into the exhaust duct rather than installed as a separate floor-standing treatment stage. The solution is designed for retrofitting into existing exhaust systems and for use downstream of different NOx-generating abatement technologies. "Fabs cannot treat emissions, energy use and space as separate challenges. With ALCEA, we place a high-performance secondary DeNOx stage where it creates the most value - directly in the existing exhaust path. The result is a retrofit-ready solution that reduces NOx by up to 95 percent while keeping the demand for floor space and utilities low. That is exactly the kind of practical innovation needed on the road to an emission-free subfab", says Guy Davies, Chief Business Development Officer, DAS Environmental Experts.？？Plasma-enhanced catalysis without special gas injectionALCEA is based on DAS Environmental Experts' proven plasma-enhanced Catalytic Technology. Reactive oxygen species are formed (ROS), which drive reactions on the catalyst surface. The process converts NOx into more highly oxidized, water-soluble nitrogen compounds that can subsequently be removed in a downstream central wet abatement system. The dry-oxidation process requires no injection of special gases and the catalysts are reusable. Depending on NOx concentration, prior treatment and plasma power, ALCEA handles volume flows of up to 5,000 standard liters per minute and achieves NOx reduction of up to 95 percent. Specified power consumption is up to 3.2 kW, depending on the NOx concentration. The system supports up to two catalyst ducts for dual systems or two individual local scrubbers. Process cooling water, reusable catalysts and a design geared toward low maintenance requirements and downtime support integration into ongoing fab operations.Developed in one of the world's leading semiconductor ecosystems, ALCEA was created in collaboration with Industrial Technology Research Institute (ITRI), Taiwan's premier applied-technology research institute. The DAS Environmental Experts engineering team in Taiwan played a central role in the development.The project combines applied research, local engineering expertise and proximity to semiconductor customers. It also represents a significant expansion of the company's waste gas treatment portfolio, adding a compact post-combustion DeNOx option for new and existing fab installations. The market launch at SEMICON Taiwan underscores the role of DAS Environmental Experts' regional teams in customer-oriented innovation and local value creation. Visitors can learn more about ALCEA and the company's wider portfolio for waste gas and wastewater treatment during SEMICON Taiwan 2026. For more information, please visit DAS Official Website and product detail page. 

Interested in knowing how to solve the microcrack problem in through-glass via (TGV) fabrication? Interested in knowing how to supply 1,000 Watts, 1 Volt and 1,000 Amperes electricity to semiconductor IC chips in an AI multichip package? Interested in knowing how to increase the glass panel size for manufacturing AI multichip packages? If so, visit iCometrue® at Booth M0957, Hall 1, 4F, Taipei Nangang Exhibition Center during SEMICON Taiwan 2026!Benefiting from their excellent thermal, mechanical, and electrical properties, glass substrates have emerged as a promising platform for large-size, high-performance AI multichip packages. At SEMICON Taiwan 2025 last year, iCometrue® exhibited the Through-Polymer-Via (TPV) Connector, a novel technology that provides vertical interconnection in Glass Cores for use in Glass Interposers and BGA substrates to solve the microcrack problem in glass substrates caused by TGV fabrication.At SEMICON Taiwan 2026 this year, iCometrue® plans to exhibit solutions for delivering over 1,000 W and over 200 A of power supply to the high-performance AI multichip package. The solutions include:(1) Embedding Cu Blocks in Glass Substrates for Power/Ground DeliveryCu blocks are used to replace TPVs/TGVs for power/ground delivery. This approach significantly reduces the number of TPVs/TGVs originally used for power/ground delivery through the glass substrate by 80%, thereby lowering fabrication complexity, improving manufacturing yield, and reducing manufacturing costs.A current high-performance AI multichip package, comprising GPU chips and HBM modules, has more than 10,000 I/Os for power, ground, signal, and clock distribution, which requires more than 10,000 TGVs/TPVs in the glass substrate. 80% of these TGVs/TPVs in the glass substrate are used for power/ground delivery. Using Cu blocks to replace TPVs/TGVs for power/ground delivery results in an 80% reduction in the number of TPVs/TGVs, thereby lowering fabrication complexity, improving manufacturing yield, and reducing manufacturing costs. Nowadays high-performance semiconductor IC chips in AI multichip packages typically require more than 1,000 W of power. Since power (P) is given by P=I×V, a 1 V operation voltage of semiconductor IC chips corresponds to a current over 1,000 A.As shown in Fig. 1, the embedded Cu blocks provide the power/ground voltage and current paths that would otherwise require a large number of TPVs or TGVs in the glass substrate. The remaining TPVs/TGVs (approximately 20%) are reserved for signal and clock transmission. Consequently, the embedded Cu blocks significantly reduce the number of TPVs/TGVs in the glass substrate.The formation of embedded Cu blocks in glass substrates is achieved by inserting Cu blocks into pre-formed large holes in the glass substrate. This process is similar to the TPV Connector embedding process in glass substrates previously disclosed at SEMICON Taiwan 2025.(2) Packaging Voltage Converter/Regulator (VCR) chips in AI Multichip PackagesThe VCR chips are packaged vertically under and close to the GPU chip within the AI multichip package. The embedded VCR chips convert the 1,000 W, 48 V, 21 A power supply from external circuits to 1,000 W, 1 V, 1,000 A for the GPU chip. As shown in Fig. 1, copper blocks provide a low resistance power delivery system from external circuits to the embedded VCR chips, and resulting in reduction of the heat generation.(3) Embedding Si Bridges, DTCs, and VCR chips in the Frontside Interconnection Scheme Over the Glass SubstrateAt SEMICON Taiwan 2025, iCometrue® demonstrated that Si bridges and DTCs are embedded in large holes within the glass substrate. Here in Fig. 1, iCometrue® shows that Si bridges, DTCs, and VCR chips are instead embedded in the frontside interconnection scheme over the glass substrate, while the TPV connectors and copper blocks are embedded in large holes in the glass substrate. This approach further simplifies the fabrication of the AI multichip package using a glass substrate.(4) Installing Electrical/Optical Connectors at the Edges of the AI Multichip PackageWhen glass substrates are used for multichip packaging, power and signals are usually input and output via the solder balls on the bottom of the multichip package through the backside interconnection (under the glass substrate), TPVs/TGVs (in the glass substrate), and the frontside interconnection (over the glass substrate) to the semiconductor chips. As discussed above, the fabrication of TPVs/TGVs is one of the major challenges in glass-substrate technology. To solve this problem, iCometrue® has introduced an innovative architecture that enables a large-size System-on-Panel (SOP) multichip package using a thick glass substrate without TPVs/TGVs.As shown in Fig. 2, power and signals are delivered through electrical and/or optical connectors located at the edges of the multichip package rather than through solder balls on the bottom of the package. The glass substrate is used as a panel-level fabrication platform and remains in the final package to provide mechanical support. An interconnection scheme (metal line and polymer) is built on the glass substrate, with electronic components such as interconnection bridges, integrated passive devices (IPDs), and VCR chips embedded within it. Semiconductor chips (CPU, GPU, ASIC, HBM) are then flip-chip bonded onto the interconnection scheme above the glass substrate. Electrical and/or optical connectors, together with passive components, are mounted on the top surface of the interconnection scheme using surface-mount technology (SMT).Credit:iCometrueBecause power and signals are supplied by the edge connectors instead of bottom solder balls, signal transmission and power distribution from the edge connectors to semiconductor chips are through the interconnection scheme. Consequently, no TPVs or TGVs are required in the glass substrate, enabling large-size System-on-Panel (SOP) packages. Further, since no TPVs or TGVs are required, a thicker glass substrate can be used, which greatly reduces the bending of the glass panel. Thereby, the size of the glass panel used in the fabrication can be greatly increased.More than Moore: The Use of Glass Substrates for Multichip PackagingiCometrue® is pioneering a new era of advanced multichip packaging by introducing glass substrates with embedded TPV Connectors and Cu blocks, providing a practical and scalable alternative to conventional TGV-based processes. Further, embedding Si bridges, DTCs, and VCR chips in the frontside interconnection scheme over the glass substrate simplifies the fabrication of the AI multichip package. Combined with the TPV/TGV-free thick glass substrate architecture for System-on-Panel (SOP) packaging, these technologies establish a foundation for the next generation of multichip integration, extending Moore's Law into the era of glass-based system packaging and accelerating the advancem

Rapid evolution of High-Performance Computing (HPC) and artificial intelligence chips for Hyperscalers and tech giants continue pushing large sized silicon demands. As a core element of semiconductor value creation, advanced packaging technology is scaling the stacking of more computing cores, more high-bandwidth memory, as well as the adoption of modular chiplet integration to overcome physical boundaries. Leading semiconductor manufacturers are expanding package dimensions to unprecedented footprints, currently reaching sizes of 100, 120, with projections moving beyond 180 mm to support large-format AI-driven advanced packages.The semiconductor industry is responding and shifting toward solutions that combine large-scale mass production with large-format packaging capabilities. Square sized substrates offer a distinct area utilization advantage to accommodate more large-form-factor chips simultaneously by moving away from round wafers to large rectangular panels. This is improving cost efficiency and addressing the challenges of thermal warpage and high-density interconnects associated with massive AI packages.Glass substrates are emerging as a key technology for advancing panel-level packaging from pilot experiments to active equipment qualification and commercialization verification. Consequently, Redistribution Layer (RDL) wet process and ECD equipment has become a critical driver of this transition and a key step in glass substrate manu-facturing. Key production tools including Electrochemical Deposition (ECD), cleaning, developing, etching, and stripping are not only vital to glass core substrate manufacturing, but also central to achieving high yields and mass production capabilities in advanced packaging technologies such as fan-out panel-level packaging (FOPLP) and Chip-on-Panel-on-Substrate (CoPoS). The wet processing equipment has garnered significant market attention.Omni production platform supports cross-sized substrates in 310, 510 and 700mm panelManz Asia, has successfully delivered Omni 310 system, which is the world’s first $310\text{mm} \times 310\text{mm}$ ECD wet chemistry system in early 2026. The system uses an electrochemical deposition module as its core, combining wet processing tools including cleaning, developing, plating, etching, stripping, and dual mechanisms support for both spin and spray operation. This new platform addresses the adaption to varying rectangular substrates.At SEMICON Taiwan 2026, Manz Asia expanded its portfolio with the launch of the cross-sized Omni series production systems. Engineered for varying panel dimensions, packaging architectures, and strict process requirements, this series feature the Omni 310, Omni 510, and Omni 700 to deliver optimized panel-level packaging (PLP) solutions across 310mm, 510mm, and 700mm panel sizes to meet the requirements of advanced PLP technology roadmaps including FOPLP, CoPoS, and Glass core TGV manufacturing.Take early-move positioning for Glass Core substrate aiming to tackle Through-Glass Via challengesRapid advancements in CoPoS are driving the shift from organic substrates to Glass Core, with TGV metallization, seed-layer formation, and copper via filling emerging as key process challenges. The Omni Series RDL platform integrates glass surface modification, cleaning, electroless copper plating, and electroplating to enhance copper adhesion and enable reliable TGV metallization and filling. Major Benefits of Omni series include.High performance ECD technology: The system offers excellent capabilities for filling high-aspect-ratio through-vias. When combined with an optimized seed layer and specialized plating chemistry, this process enables void-free via filling, delivering a highly stable and critical solution for electroplating on glass carrier substrates.High-precision glass etching technology: Featuring robust glass micro-machining capabilities, this technology supports the processing of 0.4 mm glass substrates and the creation of $20\ \mu\text{m}$ micro-vias. It offers TGV process capabilities with aspect ratios of up to 1:20, providing a critical advantage for achieving deep, fine-featured vias. Therefore, the system addresses the challenges of high-density TGV designs and marks a milestone in establishing a mass-production platform for next-generation packaging architectures.Empowering Heterogeneous Integration with advanced RDL for High-Precision Multi-Layer InterconnectionWith 40 years of in-house R&D expertise in RDL processing, Manz Asia has developed extensive expertise across PCB, IC substrate, display panel, and semiconductor packaging applications, and is now building strong collaborations with global IDM and OSAT clients. By helping customers accelerate key process iterations and transition smoothly to mass production, Manz Asia plays an active role in the global RDL processing and panel-level packaging supply chain.Designed for next-generation advanced packaging technologies like CoPoS, FOPLP, and Glass Core TGV, the debut of the Omni series production systems helps customers accelerate their transition from R&D validation to mass production. To learn more about Manz Asia production systems and product offerings, please visit the booth M1248, 4th Floor, Hall 1, Nangang Exhibition Center at SEMICON Taiwan 2026. You can also view detail product information on the official website.

Keywave Technology is a fabless semiconductor company founded in December 2022 that specializes in radio frequency (RF) integrated circuit (IC) design and advanced radar sensing solutions. Capitalizing on the explosive growth of Edge AI and opportunities for technological innovation, the company builds ultra-low-power microwave radar chips, modules and spatial sensing devices to track multiple targets with centimeter-level precision spatial positioning applications.Keywave Technology currently business focuses primarily on the UK market, where it has achieved significant success in projects spanning lighting, energy-saving systems, HVAC optimization, and smart applications involving precise occupancy tracking, smart environmental sensing and human-machine interaction.Jenny Cheng, founder and CEO of Keywave, established an office in Zhubei as early as 2023 and marked a strategic expansion into Taiwan's core semiconductor and electronics ecosystem. Recognized strong growth of Taiwan’s electronics manufacturing and semiconductor market, she formally launched an "Asia Business Division" team in 2026 with over 20 members.Following collaboration and engagement with major Taiwanese electronics manufacturing, and OEM/ODMs, Keywave has developed two radar sensor product lines, operating at 5.8 GHz and 24 GHz targeting markets such as AI robotics, smart spaces, smart buildings, automation, and edge AI sensing. Through proof-of-concept (PoC) initiatives and product design, the Keywave R&D team has focused on applications requiring high-precision spatial sensing and trajectory tracking. These innovative products, characterized by high accuracy, rapid sensing capabilities, energy efficiency, and cost-effectiveness. Now these solutions are being officially introduced to Taiwan’s industrial internet of things (IoT) and automation sector, paving the way for new business opportunities.MP Kan, VP of Technology and CTO at Keywave, outlined the shortcomings of traditional microwave radar and infrared (PIR) sensing technologies. Benchmarked against radar devices from leading global analog integrated circuits (ICs) manufacturers, he identified the primary drawbacks of these existing solutions: false detections leading to unintended activations, a technical inability to detect motionless objects or resting human bodies, and issues regarding high costs and excessive power consumption.In contrast, Keywave KW007, the compact 5.8GHz ultra-low-power radar sensor, achieves exceptional efficiency by drawing only 30µA to 100µA of operating current, enabling continuous motion detection for years on a single AA battery depending on sensitivity and the selected detection distance.This exceptional energy efficiency relies on smart sensing algorithm with proprietary multi-dimensional "Space and Time" sensing technology. This approach differs from traditional radar designs, which utilize high-performance DSP chips and extensive memory, resulting in inflated costs and high power consumption.In June 2026, Kan was invited to France to attend the inaugural European Semiconductor FSNP Meetup. Held on June 4, 2026, at Château de Seguin near Bordeaux, this was an exclusive, invitation-only event for the semiconductor industry, co-hosted by the European chip R&D platform EuroCDP and Silicon Catalyst.EU. He presented this ultra-low-power microwave radar sensing technology based on time-and-space correlation algorithms. The technology’s key strength lies in its integration of proprietary "Spatial Intelligence" and trajectory tracking, enabling it to accurately distinguish actual human movement from environmental noise in dynamic settings. It currently supports a sensing range of up to 20 meters and effectively prevents false triggers caused by natural wind, indoor fans, vibrations, or environmental noise.By combining radar sensors with AI technology, Keywave KW307, a 24GHz human presence and occupancy sensing module, enables the development of advanced, intelligent applications capable of detecting not only people and objects but even micro-motions like typing, breathing, or minor gestures. Given the regulatory restrictions in EU’s General Data Protection Regulation (GDPR) and California's CCPA/CPRA regarding the major concerns of camera-based systems capturing real-person images or personal identifiers, Keywave’s radar sensors have secured a significant market advantage by measuring motion, distance, and velocity.These microwave radar sensors facilitate applications such as office occupancy monitoring, object trajectory analysis, and climate and lighting control, while integrating seamlessly with the Industrial IoT devices, robotics, and smart home sectors to rapidly expand the scope of smart use cases. Kan also revealed that the next-generation radar sensor currently under development aims to push detection boundaries from a few hundred meters to several kilometers. This will explore the business potentials for deeper integration with drone and robotics applications to assist autonomous systems with spatial awareness and reliable presence detection in variable or low-light conditions.The most impressive technological breakthrough of Keywave Technology lies in its ability to achieve precise stationary presence detection and micro-motion tracking by analyzing the minute chest movements caused by breathing, even when a person is completely motionless. The current popular demonstration of Smart Spaces include powering privacy-compliant occupancy tracking for automated lighting and optimized HVAC adjustments. There are more use cases in the industrial controlling and detecting systems.The company is currently actively forging partnerships across various sales channels, including IC distributors, ODM/OEM manufacturers, and system integrators. In addition to offering engineering evaluation kits, development boards and support to technical teams, Keywave is seeking strategic partners to collaborate closely on the co-design of new applications with hardware and software system integrators.For further viewing the ultra-low-power radar porducts of Keywave, the company will exhibit at Microelectronics UK 2026, taking place at ExCeL London on September 29–30, 2026. The showcasing booth stand is located at Stand G16, ExCeL London, Royal Victoria Dock. At Keywave, we have been working on exciting new developments designed to help our partners navigate complex engineering challenges, optimize performance, and drive innovation. Visiting our booth will give you an exclusive look at our latest product demonstrations, upcoming technology roadmap, and a chance to speak directly with our technical experts.Credit:Keywave TechnologyKeywave radar sensor accurately tracks and records the movement trajectories of individuals.Credit:Keywave Technology

This year's SEMICON Taiwan will be packed with discussions about artificial intelligence and the on-wafer challenges it's creating, where the advanced node and emerging technology worlds collide. And at the center of it all is the need for better process control at a reduced cost-of-ownership (CoO).Right now, manufacturers are being told to buy high-priced tools designed for the front-end advanced node world - often delivering more performance than needed at a CoO that breaks the bank. It's time to break the cycle and deliver what customers want and need at a CoO that is designed to meet the needs of their business and not simply the needs of the OEM.Enter Onto Innovation.Take control of your process and break free from costly, unnecessary platforms and patchwork solutions that prevent you from achieving truly connected process control.Here's how Onto Innovation fights the status quo and puts manufacturers in control.Advanced Node Logic: Controlling Structures at the Limits of PhysicsAt the leading edge, 3D architectures are evolving fast. Gate-all-around (GAA) nanosheets require control of individual sheet dimensions, while future complementary field-effect transistor (CFET) structures will intensify 3D metrology requirements. Both demand precise nanowire control with the data richness and enhanced signal-to-noise ratio (SNR) needed to extract more than a single dimension from a single measurement.Powered by Ai Diffract modeling software, Onto's optical critical dimension (OCD) portfolio provides the precision to identify dimensional drift in complex GAA and CFET structures. Onto's films metrology portfolio measures the ultra-thin oxide, high-k metal gate, and P/N metal stack films that make up these devices. Together, these metrology solutions help manufacturers catch process drift before it becomes a downstream issue.Advanced Memory: Keeping Pace With Vertical ScalingAs 3D DRAM and 3D NAND scale vertically and device density increases, metrology has to keep pace. Manufacturers face increasingly stringent requirements for high spectrum resolution and sensitivity, and Onto's OCD and films metrology portfolio delivers the tools to stay in control as memory scales.Silicon Photonics: Controlling a Fundamentally New Kind of DeviceSilicon photonics (SiPh) and co-packaged optics (CPO) are scaling toward broader high-volume manufacturing (HVM) adoption. These architectures can integrate laser sources, waveguide-based silicon chips, micro-lenses, and opto-electronic converters, with each introducing unique process-control challenges. Defects can show up anywhere along the optical path - in the V-grooves and micro-lens arrays that couple and align light, the waveguides that route it, the EEL/VCSEL devices that generate it, and the module-level packaging (through glass vias, bump, hybrid bonding, and reflectors) that holds it all together. Any of these defects can negatively impact yield and performance. Onto's metrology and inspection portfolio enables manufacturers to address these key touchpoints with confidence.Materials Intelligence: Control That Starts Below the SurfaceNot every problem appears as a visible defect. Charge trapping, interface states, dopant profiles, and crystalline defects can erode device performance and reliability long before a part reaches test – often beyond the reach of standard metrology recipes. Onto's materials intelligence tools are built for this layer of control: FAaST for charge and interface characterization, CnCV and QUAD for yield-critical electrical insights, Aspect S for material and structure characterization of high aspect ratio (HAR) trenches and TSV, and Celero PL for crystalline defect intelligence. With Onto, manufacturers are able to identify the variations dimensional measurements alone cannot see.Advanced Packaging: Managing Complexity Where Device Types ConvergeLogic, memory, and increasingly photonics come together in an advanced package to act as one system. Process steps like hybrid bonding, TSV, silicon thinning, and copper pad recess and dishing/topography control introduce errors that don't exist in front-end flows. Copper that protrudes or recesses even slightly at a bond interface, for example, can undermine an otherwise perfect hybrid bond; this is why hybrid bonding requires tight control of surface topography, including copper pad recess and dishing/topography, along with inspection designed to catch the sub-micron, low contrast, and non-visible defects standard inspection tools can miss. Interposers, meanwhile, introduce their own set of challenges one layer down, where measuring HAR deep trench capacitors and TSV is as demanding as it is in any 3D memory stack, and where high-speed infrared (HSIR) inspection is needed to catch defects below the surface.This need for visibility is just as important, if not more so, in an AI package. Each component in an AI package- GPU or CPU, multiple HBM stacks, an interposer, a panel substrate, and CPO - is a process control touchpoint. Onto's portfolio addresses these directly: logic OCD and film metrology for the GPU/CPU, HBM bump and RDL inspection for the memory stack, interposer inspection for the layer connecting them, panel lithography and inspection for the substrate, and SiPh/CPO module inspection wherever optics are integrated - all tied together by process control and analytics software.Dragonfly G5: One Platform for Multiple Device TypesThe Dragonfly G5 system shows what taking control across device types looks like. The system delivers sub-micron defect sensitivity down to 150nm, with best-in-class throughput across front-end, back-end, and advanced packaging applications. That versatility extends beyond traditional wafer-based manufacturing. Specialty and photonics opportunities are evaluated by application, on a single platform that handles wafers and 310×310mm panels, including glass.This unrivaled versatility is the result of several complementary inspection technologies on one platform, each one designed for a different kind of defect: brightfield and darkfield imaging for standard inspection, 3Di technology for bump metrology, a new illumination mode for sub-micron, low-contrast defects (e.g. CMP, hybrid bonding), Clearfind technology for non-visible defects, and HSIR inspection for sub-surface defects. Outfitted with TrueADC Turing machine learning classification software, the Dragonfly G5 helps manufacturers reduce nuisance defects and improve defect matching and classification accuracy.The result is a platform that follows manufacturers across device types rather than forcing them to qualify a different tool for each type. The same underlying system supports front-end and back-end inspection, advanced packaging steps like hybrid bonding and 2.5D integration, and selected specialty/photonics inspection applications.Taking Control, Device by DeviceAdvanced node logic, advanced memory, silicon photonics, advanced packaging, critical films, and AI packages feature different physics, materials, and failure modes. Onto's approach to each is the same: give manufacturers a clear, connected view of their process so problems are addressed before they become expensive.That's what taking control of your process really means - not one tool built for one device, but a portfolio designed to give manufacturers visibility and confidence across the full range of their products.SEMICON Taiwan attendees can find the Onto team at Booth L0728, September 2-4. Stop by and learn how comprehensive process control solutions can help you take control of your process, yield, and future roadmap.

At SEMICON Taiwan 2026 Booth T9116, SiliconAuto will showcase automotive-grade silicon solutions for Physical AI, developed through collaboration across Taiwan's world-leading semiconductor ecosystem. Visitors can experience live demonstrations of technologies designed to power future robotics and autonomous driving applications. The solutions are built on the XMotiv M3 microcontroller and high-performance computing (HPC) platforms used in intelligent vehicles and robots.Throughout the exhibition, the SiliconAuto team will be on hand to discuss practical approaches to Physical AI development. Topics range from semiconductor architecture and system design to multi-die integration and packaging. Visitors can also get hands-on with XMotiv M3 developer kits for robotic motion control, automotive body control, and safety orchestration.Automotive-Grade Silicon, Purpose-Built for Safe and Secure Physical AIExperience SiliconAuto technologies in action through three demonstrations, spanning robotics, autonomous driving, and high-performance computing. First of all, the XMotiv M3 as an ASIL-B Robotics Controller. In collaboration with Nexuni, a Taiwanese robotics developer focused on bringing AI-powered robots into practical, everyday applications, SiliconAuto is debuting a robotic motion control developer kit. XMotiv M3 controls dynamic stabilization through joint actuators. The demonstration highlights XMotiv M3's high-speed interface capabilities. These capabilities enable real-time control. ASIL-B compliance lays the safety and security foundation.Secondly, XMotiv M3 for Autonomous Driving. See how MCU XMotiv M3 works alongside ZF's I/O interface chip to support autonomous driving capabilities up to Level 4. This autonomous driving solution was first unveiled at Embedded World 2026 where it received the Embedded Award in the SoC/IP/IC Design category. The solution demonstrates XMotiv M3 performing safety orchestration, including system management and security functions.Moreover, the Physical AI Multi-Chiplet System. Get an exclusive preview of SiliconAuto's next-generation Physical AI inference solution. The solution is built on an automotive-grade high-performance computing (HPC) chiplet architecture, designed to meet the demanding requirements of future autonomous vehicles and advanced robotics platforms. The demonstration is powered by the SiliconPilot digital twin, which provides a pre-silicon model for validation and development.As Physical AI drives the emergence of autonomous vehicles and robots, SiliconAuto is helping customers bridge the gap between AI thinking and physical action. Through automotive-grade silicon solutions, built on XMotiv M3 microcontroller, high-performance computing (HPC) platforms, vehicle-to-everything connectivity solutions, and collaboration across Taiwan's world-leading semiconductor ecosystem, the company is enabling the next generation of safe and secure Physical AI systems. To know more about SiliconAuto, please visit during SEMICON Taiwan at Booth T9116, Level 7, TaiNEX Hall 2 or visit offcial webiste. 

Tescan will participate in SEMICON Taiwan 2026 from September 2 to 4 at Booth R8201, 4F, Taipei Nangang Exhibition Center Hall 2 (TaiNEX 2). Under the theme "Streamlined Failure Analysis for Advanced Packaging," Tescan will present a correlative workflow that connects defect localization, rapid access to regions of interest (ROIs), site-specific sample preparation, and nanoscale characterization.Chiplet architectures, heterogeneous integration, advanced packaging, high-bandwidth memory (HBM), and wide-bandgap power devices are increasing structural complexity and introducing more diverse material stacks. As critical defects are often buried within packages or devices, failure analysis (FA) laboratories need an efficient end-to-end workflow that preserves sample context from non-destructive inspection through root-cause analysis.From Defect Localization to Nanoscale AnalysisTescan structures the workflow across four stages: Inspect, Access, Prepare, and Analyze. Tescan UniTOM HR 2 micro-CT provides non-destructive 3D imaging of internal package structures, warpage, and potential defects. Tescan FemtoChisel then uses gas-assisted femtosecond laser processing to expose buried ROIs, followed by precise cross-sectioning and sample preparation with Tescan SOLARIS X 2 plasma FIB-SEM under real-time SEM guidance. Tescan TENSOR 4D-STEM completes the workflow with nanoscale structural and materials characterization.By maintaining defect location and sample context across successive stages, the integrated workflow reduces repeated localization, rework, and unnecessary sample transfers. This helps R&D, process engineering, yield enhancement, and high-volume manufacturing (HVM) teams shorten time-to-answer and improve confidence in analytical results.Femtosecond Laser Processing Accelerates Workflows for Large, Complex SamplesDesigned for semiconductor sample preparation and failure analysis, Tescan FemtoChisel supports cross-sectioning, decapsulation, delayering, cavity preparation, and large-volume material removal. Gas-assisted femtosecond laser processing increases throughput while preserving the structural integrity and surface quality required for downstream high-resolution SEM, FIB-SEM, or TEM/STEM characterization.FemtoChisel Forum Presentation: From Hours to MinutesOn 2026, September 4 from 15:05 to 15:30, Hervé Macé, Semiconductor Solution Sales Development Director at Tescan, will present at the Semiconductor Advanced Inspection and Metrology Forum in Room 402 on the fourth floor of TaiNEX 1.Tescan FemtoChisel: From Hours to Minutes: High-Throughput Gas-Assisted Femtosecond Laser Workflows for Advanced Semiconductor Analysis and CharacterizationThe presentation will highlight how gas-assisted femtosecond laser processing accelerates sample preparation for large structures and complex material stacks while maintaining the quality required for downstream high-resolution characterization.Explore the Workflow at Booth R8201Tescan will host SPIN. MATCH. ENJOY. at Booth R8201 from 10:00 on 2026, September 2 and 3. Visitors can match Tescan technologies with their signature drinks while learning how non-destructive inspection, laser-based ROI access, and FIB-SEM sample preparation work together. Tescan specialists will also be available to discuss real-world failure analysis challenges and application requirements. Learn moe about Tescan at SEMICON Taiwan 2026 here.

Global technology and innovation leader ASMPT will showcase its advanced packaging portfolio at SEMICON Taiwan 2026, taking place from September 2 to 4 in Taipei. At Booth L0716 (TaiNEX 1, Level 4). ASMPT will be presenting technologies supporting next-generation AI, High-Performance Computing (HPC), Co-Packaged Optics (CPO) and photonics applications under the theme "Empower the Intelligence Revolution."  Reflecting its continued commitment to Taiwan, one of the world's leading semiconductor hubs, ASMPT is also strengthening its local leadership and customer engagement capabilities.Taiwan remains a key center for semiconductor innovation and advanced packaging. Working closely with customers across the region, ASMPT supports the industrialization of next-generation semiconductor technologies, helping bring advanced concepts into reliable, high-volume manufacturing and enabling the innovations that power the AI era.As part of its continued investment in Taiwan, ASMPT appointed Johnny Fan as General Manager, Country Head & Head of Sales, Semiconductor Solutions Taiwan, further strengthening its local leadership and customer support."Taiwan is at the forefront of semiconductor innovation, particularly in advanced packaging technologies that are enabling the AI era," said Johnny Fan. "Our customers are driving some of the world's most advanced semiconductor innovations in AI, HPC and photonics. The challenge is turning those innovations into production-ready solutions at scale, and that's where ASMPT helps its customers succeed."As AI applications continue to drive demand for more powerful and efficient semiconductor architectures, advanced packaging is playing an increasingly important role in delivering the required performance, power efficiency and integration. At SEMICON Taiwan 2026, ASMPT will present solutions supporting applications in HPC, AI accelerators, silicon photonics and Co-Packaged Optics (CPO), leveraging technologies such as Thermocompression Bonding (TCB) and Hybrid Bonding.As an example of these capabilities, ASMPT will showcase its MEGA multi-chip bonding solution. MEGA combines high-precision placement with alignment accuracy of ±2μm and ±0.1°, integrated epoxy dispensing and stamping capabilities, parallel processing of multiple adhesive materials, immediate UV fixation and integrated 3D inspection of the adhesive application. Independently operating pick and bond arms, together with a flip-pick unit and integrated rotation stage, enable flexible process execution for complex multi-chip and photonics applicationsJohnny Fan, ASMPT Taiwan Country Head, drives customer engagement & local ecosystem. Credit:ASMPT

Interested in solving microcrack issues in through-glass via (TGV) fabrication? Want to learn how to supply 1,000 Watts, 1 Volt and 1,000 Amperes electricity to semiconductor IC chips in an AI multichip package while scaling up glass panel sizes? If so, visit iCometrue at Booth M0957, Hall 1, 4F, Taipei Nangang Exhibition Center during SEMICON Taiwan 2026!Glass substrates have emerged as a promising platform for large-size, high-performance AI multichip packages due to their superior thermal, mechanical, and electrical properties. At SEMICON Taiwan 2025 last year, iCometrue exhibited the Through-Polymer-Via (TPV) Connector, a novel technology that provides vertical interconnection in Glass Cores for use in Glass Interposers and BGA substrates to solve the microcrack problem in glass substrates caused by TGV fabrication.At SEMICON Taiwan 2026 this year, iCometrue plans to exhibit solutions for delivering 1,000 Watts, 1 Volt and 1,000 Amperes electricity to semiconductor IC chips in the high-performance AI multichip package. The solutions include:1. Embedding Cu blocks in glass substrates for power/ground delivery: Reducing the number of TPVs/TGVs originally used for power/ground delivery by 80%, thereby lowering fabrication complexity, improving manufacturing yield, and reducing manufacturing costs.2. Packaging Voltage Converter/Regulator (VCR) chips in the AI multichip package: Allowing high-voltage (for example, 48V) power supply input to the package and reducing power supply voltage (for example, down to 1V) within the package, based on the copper-block-based low resistance power delivery system. The innovated copper-block-based low resistance power delivery system reduces the heat generation.3. Embedding Si bridges, deep-trench decoupling capacitors (DTCs), and Voltage Converter/Regulator (VCR) chips in the frontside interconnection scheme over the glass substrate: Silicon bridges, DTCs, and VCR chips are embedded directly into the frontside interconnection scheme over the glass substrate, leaving large holes in the glass substrate dedicated to TPV connectors and copper blocks to streamline manufacturing.4. Installing electrical/optical connectors at the edges of the AI multichip package: This architecture uses electrical and/or optical connectors at the package edges for power and signal input/output, replacing the conventional power and signal routing that traditionally relied on bottom solder balls. This unleashes a TPV/TGV-free System-on-Panel (SOP) package, allowing thicker glass substrates that drastically reduce panel bending and enable larger manufacturing panel sizes.By using innovations mentioned above, iCometrue provides a scalable, practical alternative to traditional TGV processes. These breakthroughs extend Moore's Law into the era of glass-based system packaging, accelerating high-performance computing (HPC) and AI applications.