Altera Corporation announced its OpenCL (Open Computing Language) for FPGAs Early Access Program (EAP), enabling customers to get a first look at Altera's OpenCL for FPGA solution. Leveraging the open standard dramatically simplifies FPGA development by enabling teams to design their systems and algorithms in a high-level C-based framework when targeting FPGAs. As part of the EAP program, customers will be able to preview Altera's OpenCL solution and receive access to an OpenCL for FPGA training course, collateral and technical demonstrations.
OpenCL is an open standard for writing programs that execute across heterogeneous platforms, including CPUs, GPUs and FPGAs. OpenCL provides customers a significant time-to-market advantage compared to traditional FPGA development flows that require the user to design in a lower-level HDL (hardware description language). Customers joining the EAP program will see how OpenCL can simplify many of the time-consuming details of hardware design by allowing users to operate in a C-based environment and automatically generate the FPGA implementation.
In addition to simplifying FPGA development, EAP customers will also discover how using an OpenCL in an FPGA implementation provides dramatic system performance advantages. Combining an inherently parallel language with the massively parallel performance capabilities of FPGAs delivers significantly higher performance compared to alternate hardware architectures.
"There has been a tremendous amount of excitement from designers interested in integrating an OpenCL development flow with FPGAs. With very positive results from initial customers we are pleased to be able to give more customers early access to preview the solution," said Jeff Waters, senior vice president and GM of Altera's Military, Industrial and Computing division. "OpenCL enables a broad segment of designers in a variety of end markets including high performance computing, military, medical and broadcast to dramatically increase the performance of their end systems using the latest generation of FPGAs and a highly productive development flow."
Altera is currently engaged with a variety of customers to implement designs in FPGAs using an OpenCL flow. These customers have seen the productivity and performance benefits that can be achieved using OpenCL for FPGA development.
Koumei Tomida, Manager, Controller Platform Development V, Controller Development Group, at Fuji Xerox commented, "Using an OpenCL flow for FPGAs is intriguing as it gives us access to the latest generation of high-performance FPGAs, while providing us a significant reduction in time to market. Based on our initial use of Altera's OpenCL tool, we have been able to quickly and easily optimize our OpenCL kernels to target Altera FPGAs for higher performance and seamlessly integrate our design into the high-performance fabric of an FPGA."
OpenCL for Altera FPGAs training now available
Altera has partnered with Acceleware, the industry leader in OpenCL and parallel programming training, to offer a course titled "OpenCL for Altera FPGAs" which provides detailed training on the OpenCL language and how to use it with Altera FPGAs. The course is available for OpenCL EAP customers only and will be held in a variety of regions. Contact your local Altera sales representative to schedule a training session.
Joining the OpenCL for FPGA Early Access Program
Customers who join the OpenCL EAP will receive the latest information from Altera representatives on the OpenCL tool and how it works. Customers will also receive early access to product documentation and periodic information from Altera about the OpenCL program. To join, contact your local Altera sales representative: http://www.altera.com/corporate/contact/sales/worldwide/con-sales-ww.jsp
Learn more about Altera's OpenCL Program for FPGAs: www.altera.com/b/opencl.html
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