Samsung Electronics is keenly exploring "hafnia ferroelectrics" as a next-generation NAND flash material, with the hope that this new material will enable stacking over 1,000 layers of 3D NAND and achieving petabyte-level SSDs.
The hafnia ferroelectrics material is expected to replace the oxide-based thin films currently used in 3D NAND stacking technology, improving chip durability and stability. Samsung executives predict that its 3D NAND could stack over 1,000 layers by around 2030.
According to industry sources cited by South Korean media outlet The ChosunBiz, Samsung is intensifying the development of hafnia ferroelectrics-based 3D NAND technology in collaboration with the Korea Advanced Institute of Science & Technology (KAIST). Their R&D achievements will be showcased at the 2024 IEEE Symposium on VLSI Technology & Circuits, to be held June 16-20 in Hawaii, the US.
The emergence of 3D NAND aimed to overcome the limitations of planar NAND. In 2013, Samsung was the first to commercialize 3D NAND, which offers faster speeds, larger capacity, and lower power consumption compared to 2D NAND. However, 3D NAND technology still faces challenges.
Firstly, 3D NAND requires using thin films made from materials such as oxide/nitride (ONON) or oxide/polysilicon (OPOP). As the number of stacked layers increases, deviations between these materials grow, leading to lower production yields, reduced performance, and diminished durability.
Moreover, 3D NAND faces formidable manufacturing challenges, particularly in the etching process. As the number of layers increases, precise etching becomes more difficult. Even in the current mainstream production of 100 to 200 layers, maintaining consistent hole diameter throughout the layers of 3D NAND is proving extremely difficult.
Many companies propose using ferroelectric materials to replace the current oxide 3D NAND thin film materials as a solution. Improved stability with ferroelectric materials could make the etching process relatively easier, which is beneficial for enhancing chip performance.
