The Best AI awards were given out in two categories: artificial intelligence (AI) applications and integrated circuit (IC) design. AIYO was entered in the IC design category, but their concept – AI-powered acceleration of IC design – really straddles the two categories.
Chip design is a long, arduous process. Today's chips contain billions of transistors, and designers not only have to design them to do what they want them to do, but have to ensure that the design satisfies a large number of rules and can actually be physically produced in a foundry.
Since 2010, the number of transistors and gates has increased by nearly a hundredfold, but engineering productivity (as measured by the number of gates that a chip designer can design in a day) has increased by only about three times. This 29-times gap is set to widen even further over the next few years. In other words, it takes chip engineers more time than ever before to do their job.
The problem lies not solely in the number of components on a chip but in the complexity in how they interact. The demand for custom silicon – ICs specially designed and optimised for specific applications or customers – and the sheer number of use cases now being designed for is growing, but it is getting harder and harder to find the engineering talent for custom silicon. Specialised silicon requires specialised talent.
Tier-one design houses, like NVIDIA or MediaTek, can still find talent, but it's a different story for tier-two companies. Chip design is increasingly a bottleneck for technology companies to implement their AI-powered (and non-AI-powered) solutions.
AIYO thinks that AI can help with that. It aims to reduce the gap between tier one and tier two companies, without completely replacing human design and the need for engineers. Engineers use natural language to provide their design specifications, including the constraints and requirements that the chip must satisfy. AIYO's AI agent then generates Verilog, which is a piece of code that describes the design of digital circuits.
This Verilog must satisfy the specifications that the user set out. AIYO's agent can also optimise it along various metrics, such as for a lower power consumption, a higher performance (in other words, how fast the chip operates, as measured by its clock speed or data throughput), or a smaller area (PPA) are the most commonly invoked. Different chips prioritise these three factors (collectively known as PPA) differently, but AIYO can trade off, for example, a lower performance for a lower area and less power consumption.
AIYO's agent then performs a closed-loop verification of the design to ensure that it is feasible. The agent reviews the error logs and iterates the design until the design passes all tests. Then – at least theoretically – the design is ready for tape-out, or actual production of the circuit at the foundry. Tape-out is an expensive process, costing in the millions of dollars, so it is essential that the finalised design performs as expected.
AIYO uses RISC-V, an open-source instruction set architecture (ISAs) that has grown exponentially in popularity since its introduction in 2014; it has already been used in more than 20 billion cores. This avoids the need to pay a licensing fee to the more common (but not open-source) ISAs in use today, such as ARM or x86.
The performance of IC-design agents can be measured using a standard set of test problems. Can the agent solve the problems (i.e., design a suitable IC) on the first pass? And can it solve a different set of IC design problems eventually, after however many iterations? AIYO performs at the head of the pack in both models, a little bit ahead of NVIDIA's VerilogCoder agent and far ahead of ChatGPT, DeepSeek, and Claude.
One to two engineers are now required to design a chip, where three to five would have been needed before. Furthermore, it now takes these one or two engineers two months to design a chip (and they can test multiple designs simultaneously), whilst those three to five engineers in a traditional design house would have needed six months. This is an improvement in efficiency of roughly an order of magnitude.
AIYO is still a work in progress, and humans are needed to check for any mistakes the engine might make – human engineers' jobs are safe, at least for now. But AIYO does makes it possible to compress the iteration cycle and for even tier-two chip design companies to realise their designs with limited human resources.
One of AIYO's most pressing next steps is expanding its customer base – not only for commercial reasons, but also because this will expand their training data and thus improve their AI engine. AIYO currently has one customer who needs help designing custom FPGA (field-programmable gate array) integrated circuits. AI is, by default, a generalist, and its large language models can fail when faced with very specific use cases that it has yet to see. Helping this customer with its specific use cases can help the AI engine gain specialist skills, and the more customers that AIYO can obtain, the more versatile the tool will be.
To this end, the team is expanding the set of design problems. A large set of open-source IC design problems already exists, but AIYO is also working on building their own set of synthetic design problems.
The money from the Best AI Awards is great, says Ballard, but realistically, it is not even enough for one year's access to a top EDA (electronic design automation) tool – training AI models is expensive. He says that the biggest benefit from the awards is the people it has allowed them to meet, and in particular, the conversations they've been able to have. "They'll ask, 'Did you consider X, Y, and Z?' Sometimes yes, we have, but sometimes, we have an action item for the future."
This also gives them an opportunity to enter talks with various venture capital investors and potential Taiwanese partners. AIYO is currently working with funding provided by the co-founders themselves, but they're hoping to find a Taiwanese venture capital investor in the next few months.
Tang-Hung Po and Austin Ballard have been working on AIYO for only roughly a year. Po, originally from Taiwan and now based back in the country, obtained his master's in electrical engineering and computer science from the University of Michigan; he is the company's primary engineering lead. He brings more than 20 years of experience in SoCs (systems on a chip) and ASICs (application-specific integrated circuits) to AIYO, and was previously a director and a chief technical officer at other companies.
Ballard, an American based in Seattle but with a Taiwanese mother, brings his experience scaling operations at Meta, Amazon and TikTok to now handle anything at AIYO not related to engineering, The time difference allows them to collaborate during Ballard's evenings and Po's mornings, and their almost diametrically opposite locations, along with their different skill sets, facilitates engagement with all sorts of partners on both sides of the world. (As a side benefit, Ballard now has a business reason to visit Taiwan!)
The Best AI Awards celebrate global excellence in artificial intelligence and IC design, welcoming submissions from innovative companies and brilliant student teams. Following the success of the 2026 edition—advised by the MOEA, organized by DoIT, and executed by TCA—the prestigious competition is officially transitioning into an annual tradition.
Offering substantial grand prizes and unmatched industry exposure, the countdown to Best AI Awards 2027 has already begun. Details on the next submission cycle, prize tiers, and eligibility rules will be released soon. Connect with us on LinkedIn for the latest official updates and application alerts.