SNUG Taiwan 2014 was recently hosted by Synopsys Taiwan in Hsinchu, with representatives from almost 30 heavyweight customers sharing ideas and presenting their design and research achievements. Senior managers from important partners such as Taiwan Semiconductor Manufacturing Company (TSMC), MediaTek Inc., United Microelectronics Corporation (UMC), and Imagination Technologies also gave keynote speeches at the event.
SNUG: The largest and most comprehensive advanced design technology platform in Taiwan
The two-day event covered topics such as physical design, synthesis, testing, circuit simulation, verification, debugging, systems, IP, hardware emulation, and FPGA-based prototyping. The event, which was attended by over 1,200 IC design engineers, saw nearly 30 heavyweight semiconductor firms present their technological achievements. SNUG is currently the largest and most comprehensive platform in Taiwan where insights into advanced IC design technologies are shared and discussed.
In his speech, Robbins Yeh, Chairman of Synopsys Taiwan, noted that the Taiwan branch of the US-based company was established 23 years ago. SNUG Taiwan, which was first held in 2001, has been growing with Taiwan's semiconductor industry and this year marks the event's 14th anniversary. Synopsys' 2014 global revenues are estimated to exceed US$2 billion, ranking number 16 among all software firms worldwide and marking an important milestone for the EDA sector.
Synopsys cultivates the largest R&D team of all foreign software firms in Taiwan
Currently, Synopsys has more than 370 R&D personnel in Taiwan, which is the biggest R&D team among all foreign software firms operating in Taiwan. With close collaboration with academia, business partners, and research organizations, Synopsys demonstrates continuous commitment to the Taiwan market.
Yeh stated that as the IT industry enters the post-PC era, firms have been working closely together, moving from division of labor vertically to vertical integration. Hence, the SNUG Taiwan 2014 set theme as "Innovation and Collaboration" to demonstrate a hope that industry players can join forces in the face of severe competition and capture new business opportunities with innovative designs.
In his speech, Paul Lo, Senior VP of Synopsys Design Group, introduced innovative technologies in P&R (place-and-route), verification, prototyping, and IP solutions.
Innovation and collaboration to help Taiwan firms overcome increasingly complex design challenges
According to statistics from market research firms, the global semiconductor market is likely to grow by 5% in 2014 and continue to grow in the next three years, driven by robust developments in the mobile, cloud computing, and Internet of Things (IoT) applications markets. In recent years, many technology firms have been striving to accelerate their own innovations, and at the same time making efforts to increase economies of scale and enhance technological prowess through acquisitions. Lo added that there are likely to be more acquisitions in the future as the cloud computing and IoT markets heat up.
The semiconductor process technology has already come to 16/14nm FinET nodes and is moving towards 10/7nm. Lo emphasized that FinET requires support from manufacturing processes, circuit simulation, physical IP, custom design, physical verification, implementation, signoff and various SoC design processes. Synopsys' design tools are ready for this type of advanced process, and at the same time it has been working closely with wafer foundry houses. Currently, there are more than 250 design projects on the sub-22nm nodes and more than 100 design projects on the 16/14nm FinET technology nodes, showing Synopsys' full support to help customers achieve designs using advanced processes.
At the same time, demand remains strong for 130/90/65/40nm mature processes as applications for automotive, medical, sensor and various smart devices become popular. Synopsys strives to incorporate advanced design functions into existing nodes to help customers achieve optimal results.
Synopsys' innovative technology fulfills advanced design need at each process node
Henry Sheng, Group Director of Synopsys, outlined the company's latest development of P&R solutions. While volume production on 18-inch wafers is expected to ramp up in 2018, according to Sheng, the ITRS blueprint also indicates that the semiconductor industry will proceed to the 7nm process technology node in 2017. Hence it is foreseeable that the industry is entering an era of extremely high quantity of extremely small transistors.
Although the industry's focus has been on continuous development of advanced technology, demand for mature technology remains strong. According to a 2013 study, although the sub-40nm advanced processes accounted for more than 60% of total wafer shipments, the 40nm and above mature processes accounted for as high as 88% of all design starts.
In particular, the markets for automotive, medical and IoT applications have been growing and these applications will mainly use mature process technology. Analog, mixed-signal, 3D-IC and MEMS technologies will play more important roles, and therefore firms need to achieve design differentiation at every process node in order to beat competitions.
Sheng stated that as design complexity increases, routing becomes more difficult and there are many rules that must be followed. Synopsys has been working toward building optimal PPA design using more advanced routing functions.
IC Compiler II and Verification Compiler: A major focus of SNUG Taiwan 2014
Synopsys' recently introduced IC Compiler II and Verification Compiler solutions were another focus of SNUG Taiwan 2014.
Sheng noted Synopsys' IC Compiler has been the industry-leading design tool. Over the past few years, Synopsys has continued developing technology to maintain the leading position of IC Compiler, and at the same time has been striving to improve the design team's productivity by devising new P&R systems.
IC Compiler II was developed to accelerate physical design by adopting a new multi-threaded infrastructure able to handle designs with more than 500 million instances. In addition, IC Compiler II incorporates important technologies of IC Compiler such as conjugate-gradient layout placer and ZRoute router.
IC Compiler II is a full chip-level design that delivers a groundbreaking 10-times increase in design throughput while reducing memory consumption by five times. The product comes with super high capacity, special timer, and analytical engine.
Yu-Chin Hsu, VP of R&D at Synopsys Verification Group, explained that as the chip complexity increases, design verification faces three challenges: scale, efficiency and cost. The industry must find more comprehensive solutions integrating previous a-la-carte tools to overcome these challenges.
Verification Compiler is a comprehensive solution that integrates the latest generation of verification technologies. The solution includes advanced debugging tools, static and formal technologies, simulation, verification IP, and coverage analysis. By integrating these technologies, the product can increase design throughput by five times and greatly improve the efficiency of debugging. This allows SoC design and verification teams to use the same product to create a complete verification process.
Furthermore, Verification Compiler is based on the industry-leading Verdi3 debug environment, featuring UVM-aware debug, transaction-level debug, HW/SW debug, power-aware debug, and interactive debug. These functions are all built together on an easy-to-use environment to greatly improve debugging efficiency.
SNUG is currently the most important technology exchange platform in Taiwan's IC design industry and Synopsys Taiwan will continue bringing in innovative technology to closely collaborate with local semiconductor design firms and manufacturers.
Paul Lo, Senior Vice President of Synopsys Design Group
Robbins Yeh, Chairman of Synopsys Taiwan
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