The rising costs of AI chips driven by advanced process technologies have continued to escalate, while the direct performance gains from these process improvements have significantly diminished. Consequently, cost-effective advanced packaging has emerged as a key focus in the semiconductor industry.
DIGITIMES believes that combining chiplets with advanced packaging technologies will be a critical strategy for enhancing the performance of high-end AI accelerators in the future. Furthermore, the integration of new materials, such as glass and silicon carbide (SiC), along with the development of novel techniques like co-packaged optics (CPO) and fan-out panel level packaging (FOPLP), will further drive the advancement of AI chips.
DIGITIMES notes that while advanced processes remain the primary method for upgrading AI chips, they are not the sole solution. Advanced packaging technology enabling heterogeneous integration between advanced chips and functional chips is gradually playing a critical role.
Chart 2: Chiplet archiecture diagram and its benefits and challenges
Chart 3: Estimated cost of chips with different sizes by packaging tech
Chart 4: Roadmap of 2.5D packaging interposer sizes, 2023V2027
Chart 5: TSMC 2.5D packaging chip integration specifications, 2025-2027
Chart 6: Material options and details of interposers and substrates in 2.5D packaging
Chart 7: Performance comparison of OE across different packaging types
Chart 8: Wafers and square carriers, and area usage improvement in chip packaging
Chart 10: Summary on routes to improve chip performance via advanced packaging

