Samsung Electronics has successfully stacked the next-gen 3D DRAM to 16 layers, twice as many as its competitor Micron.
According to reports from TheElec and ZDNet Korea, citing industry sources, Samsung has successfully stacked 3D DRAM into 16 layers. In contrast, Micron has only achieved 8 layers. However, the 3D DRAM product is currently in the feasibility stage; the goal is to realize commercialization by 2030.
The 3D DRAM uses vertical stacking, which can increase the capacity per unit area by three times, thus enabling the rapid processing of large amounts of data. Samsung aims to widen the gap with competitors in 3D DRAM technology. Compared to existing DRAM structures, 3D DRAM can include more storage cells and reduce electrical interference.
Unlike traditional DRAM, the VS-CAT style 3D DRAM is expected to be manufactured by combining two wafers, a concept similar to YMTC's Xtacking. 3D DRAM stacking is also expected to utilize Wafer-to-Wafer (W2W) hybrid bonding, a technology already utilized in NAND and CMOS Image Sensors (CIS).
At the same time, Samsung is also researching vertical channel transistor (VCT) style 3D DRAM. The industry also refers to VCT-style 3D DRAM as 4F SQUARE, with its most notable characteristic being its vertically oriented transistor structure. If Samsung successfully develops this, the die area could shrink to around 30% of the original size.
Industry sources indicated that Samsung will unveil 4F SQUARE prototypes in 2025. In contrast, Samsung's two major competitors in the DRAM market, SK Hynix and Micron have elected to develop 3D technology with a stacked cell style.
In addition, Samsung mentioned the possibility of applying Backside Power Delivery Network (BSPDN) technology to DRAM for the first time. BSPDN is considered a highly difficult technology, and Samsung plans to introduce BSPDN technology into the 2nm process by 2025.
