Cadence's solution includes a digital twin.
The increasing popularity of Advanced Driver Assistance Syms (ADAS) and Software Defined vehicle SDV is driving demand for more complex AI and software functionalities as well as interoperability and collaboration within the automotive electronics ecosystem, which poses higher requirements.
Thanks to a growing need for rapid customization of 3D-IC systems for a wide range of automotive applications, small chips have become a more attractive solution. Seamless collaboration between small chips from different IP suppliers is key.
The rapid development of automotive development means 3D-IC system developers urgently need a software development platform to enter software development early in the process while IP and small chips are still being designed.
The new solution architecture and reference designs provide standards for small chip interface interoperability. This meets critical industry needs.
Cadence's solution includes a Helium Virtual and Hybrid Studio for quickly establishing virtual and hybrid platforms, and a Helium Software Digital Twin to support large-scale adoption by software developers. The solution also incorporates leading I/O IP solutions for interfaces and memory protocols, including Universal Chiplet Interconnect Express for high-speed communication between chiplets.
Cadence is also offering a comprehensive portfolio of computational IP products. These include advanced AI solutions, Neo Neural Processing Unit IP, NeuroWeave software development kit for machine learning solutions, and DSP computing solutions.
Dipti Vachani, Senior Vice President and General Manager of Arm's Automotive Product Line, said the automotive industry is rapidly evolving. Advances in AI and software highlight the urgent need to accelerate development cycles, he added.
Arm and key ecosystem partners such as Cadence are collaborating to integrate complete design and verification technology solutions based on Arm's latest automotive enhancement technology. Arm's collaboration enables faster software and hardware development, allowing developers to build the next generation of SDV before the chip is available, significantly shortening development cycles.
Paul Cunningham, Senior Vice President and General Manager of the System and Verification Division at Cadence, said to shorten time to market when developing increasingly complex SDV, it is necessary to reduce overall system design workload and shift hardware and software development left. Virtual platforms and small chips are key drivers of automotive 3D-IC SoC development, he added.
Through close collaboration with Arm, efficiency issues in software and hardware development and verification processes can addressed, he said. This also promotes the development of automotive semiconductors in a multi-chip small-chip ecosystem, he added.
