Applied Materials and the Institute of Microelectronics (IME), a research institute under Singapore's Agency for Science, Technology and Research, have announced a five-year extension...

STATS ChipPAC has shipped over one billion fan-out wafer level packages (FOWLP), also known in the industry as embedded wafer-level ball grid array (eWLB), according to the company...

Advanced Semiconductor Engineering (ASE) and Deca Technologies, a subsidiary of Cypress Semiconductor, have announced the signing of an agreement whereby ASE will invest US$60 million...

Cadence Design Systems has announced the availability of foundry-proven IC packaging design and analysis solutions for advanced fan-out wafer-level chip scale packaging (WLCSP) and...

TSMC will be ready to roll out its 5nm process technology two years after the launch of its 7nm node, according to the pure-play foundry.

The US$18 billion semiconductor packaging materials will undergo steady single-digit unit volume growth for many material segments through 2019, including laminate substrates, IC...

TSMC is scheduled to move its integrated fan-out (InFO) wafer-level packaging technology to volume production in the second quarter of 2016. Apple will be among the first wave of...

Cadence Design Systems has announced that its Allegro system-in-package (SiP) and physical verification system (PVS) implementation technologies have been enabled for TSMC's integrated...

NANIUM S.A., a leading provider of advanced semiconductor packaging known for its innovative solutions, today announced it achieved outstanding reliability results for a Wafer-Level...

Taiwan's Xintec, an affiliate of Taiwan Semiconductor Manufacturing Company (TSMC) specializing in packaging services for CMOS image sensors as well as MEMS and fingerprint sensors,...

Taiwan Semiconductor Manufacturing Company's (TSMC) backend integrated fan-out (InFO) wafer-level packaging (WLP) technology will start contributing significantly to the IC foundry's...

Altera and TSMC have produced an UBM-free (under-bump metallization-free) WLCSP (wafer-level chip scale package) technology for Altera's MAX 10 FPGA products, according to the comp...

Image sensor packaging house Xintec will have its 12-inch wafer-level chip-scale package (WL-CSP) line ready for volume production in the second half of 2015, according to company...

Taiwan Semiconductor Manufacturing Company (TSMC) will have its backend integrated fan-out (InFO) wafer-level packaging (WLP) technology ready for 16nm chips, eyeing orders for Apple's...

United Test and Assembly Center (UTAC), a Singapore-based assembly and test company, will continue its investment in Taiwan in 2015 by setting up a 12-inch wafer-level packaging line,...