ZEISS, a global leader in optics and optoelectronics, will bring the quality discussion to the official COMPUTEX 2026 Forum stage for the first time this year, highlighting the growing role of quality in scaling AI hardware.
As demand for AI infrastructure accelerates, quality is shifting from a manufacturing support function to a direct driver of performance, yield and delivery readiness. While public attention often centers on AI models, ZEISS says reliable hardware execution is becoming a decisive factor in AI deployment.
Behind every AI interaction are massive data centers powered by thousands of GPUs. As systems scale from chip to rack, defects in semiconductor packaging, printed circuit boards (PCB/A), cooling systems and high-speed interconnects can affect uptime, deployment speed and total cost.
"With compute demand surging, manufacturers face record orders, but the challenge is delivering at scale with consistent quality," said Clive Yen, Global Head of Electronics Customer Segment, ZEISS Industrial Quality Solutions. "As systems grow more complex, quality becomes critical to reliable deployment. This is why we work across Taiwan's ODM ecosystem and the full AI server value chain to enable consistent, scalable quality."
"At scale, even small defects can become major bottlenecks," said Tonmoy Kundu, Global Head of Sales, ZEISS Research Microscopy Solutions. "Manufacturers need faster insight, tighter process control and trusted failure analysis to accelerate next-generation AI hardware."
ZEISS says it offers one of the industry's most comprehensive quality portfolios across the AI hardware value chain, supporting customers from semiconductor packaging and PCB inspection to liquid cooling, optical connectivity and final rack integration.
At the forum, ZEISS will showcase solutions for advanced high-bandwidth memory (HBM), where rising stack heights and shrinking interconnect dimensions require high-resolution, non-destructive inspection and deep defect analysis.
The company will also present metrology solutions for co-packaged optics (CPO), where ultra-tight tolerances for FAU and MPO connectors are essential to maintain alignment, coupling efficiency and long-term transmission reliability in 51.2T+ networks.
At the exhibition hall (Booth J1109 | TaiNEX Hall 1, Taipei), ZEISS will showcase technologies spanning wafer process control, advanced packaging, X-ray inspection, electron microscopy, light and digital microscopy, and coordinate measuring machines. Applications will focus on chip manufacturing, PCB reliability, thermal management systems, connector quality and L10-L11 rack mechanical parts assembly.
COMPUTEX 2026 runs June 2-5 in Taipei, where ZEISS will position quality as a foundational enabler of the next wave of AI growth. ZEISS will speak at the official COMPUTEX 2026 Forum on June 4, 4:30 p.m. to 4:55 p.m. at TaiNEX 2, Room 701, presenting "Quality Innovation Across the AI Chip-to-Rack Stack." The session will feature Tonmoy Kundu and Clive Yen.
