In a fierce race with TSMC and Intel to develop next-generation chipmaking processes, Samsung Electronics is reportedly accelerating its adoption of BackSide Power Delivery Network (BSPDN) technology, aiming to integrate the technology into its 2nm process by 2025, a move that could reshape the foundry market landscape.
According to industry sources cited by Korean media outlet ChosunBiz, Samsung has achieved better-than-expected results for its BSPDN technology development. The company's utilization of two distinct Arm kernels has reduced the chip area by 10% and 19%, respectively, while enhancing chip performance and efficiency.
Traditionally, chip designers place power supply lines on the front side of the wafer to facilitate the manufacturing process. However, as the circuits become increasingly intricate, putting circuits and power delivery lines on one side becomes difficult. In addition, shrinking gaps between circuits can lead to electrical interference, further complicating chip design and manufacturing.
Accordingly, BSPDN emerges as a solution to these limitations. With power lines placed on the backside of the wafer, BSPDN separates the space for intricate circuitry from the power delivery, thus maximizing power efficiency and improving chip performance. This technology can also effectively reduce the chip area, facilitating further miniaturization of mobile application processors (APs).
Bolstered by its BSPDN development exceeding expectations, Samsung is on track to expedite commercialization from its original target of 2027. Initial reports indicated Samsung would implement BSPDN technology in the 1.7nm process, but the latest rumors suggest an earlier integration into the 2nm process by 2025.
Despite Samsung surging ahead with its BSPDN development, Intel is currently believed to be the leader in this field. The company is aiming for mass production using its BSPDN technology in 2024, targeting integration into its 20A (2nm) process chips. Intel has even created a dedicated tech brand, "PowerVia," to highlight its BSPDN prowess. Meanwhile, TSMC plans to incorporate BSPDN technology into its sub-2nm process.
