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TSMC's 3nm process at full capacity, led by Intel's Lunar Lake and Apple's iPhone 16 launch

Monica Chen, Berlin; Jingyue Hsiao, DIGITIMES Asia 0

David Feng, VP and GM of Clieng Segments at Intel, and Lunar Lake. Credit. DIGITIMES

With major IC design houses like Intel, Apple, and Qualcomm launching new products amid rising electronics demand, TSMC's 3nm capacity utilization has consistently stayed at 100%, which is expected to positively impact the company's third-quarter results.

As PC and smartphone inventory corrections wind down and demand gradually recovers, TSMC's 3nm capacity utilization has remained at full capacity. This high utilization level is fueled by robust demand from key clients like Intel, Apple, Qualcomm, and MediaTek, who have been introducing new products using the 3nm process since September.

Market estimates indicate that the 3nm process, which commands nearly US$20,000 per wafer, contributed 15% of TSMC's total revenue in the second quarter, amounting to approximately NT$101 billion (US$3.14 billion). With major clients ramping up new product launches in the second half of the year, the revenue share from the 3nm process is projected to grow significantly. Consequently, TSMC's revenue and gross margin for the third quarter and the full year are expected to exceed previous forecasts, positioning the company for continued high growth in 2025.

In addition to strong demand for HPC, TSMC is also seeing a surge in consumer electronics. The utilization rate of its 5nm and 4nm processes has remained at 100% since the beginning of the year, and the high-margin 3nm process is also fully loaded.

Intel's launch of the Core Ultra 200V series, manufactured using TSMC's 3nm process, marked a significant milestone. As it is codenamed, the Lunar Lake chip consists of a compute tile and a platform control tile, interconnected by Intel's Foveros advanced packaging technology and featuring integrated memory.

The compute tile, manufactured on TSMC's 3nm process, incorporates new E-cores and P-cores with redesigned microarchitectures for both high performance and efficiency. It also features the new Xe2 GPU architecture, NPU 4, and an image processing unit (IPU) for enhanced graphics, AI computing, and multimedia processing capabilities. The platform control tile, manufactured on TSMC's 6nm process, integrates the latest communication standards such as Wi-Fi 7, Bluetooth 5.4, PCIe Gen5, PCIe Gen4, and Thunderbolt 4.

Apple, TSMC's longstanding largest customer, continues to be a major revenue contributor. After the launch of MacBook, iPhone 15 Pro, and iPad Pro models utilizing the 3nm process, Apple is poised to unveil its new iPhone 16 series, which will fully adopt the 3nm technology, on September 10th.

In October, MediaTek and Qualcomm are expected to launch their 3nm chips. Qualcomm will hold its annual Snapdragon Summit on October 21-23, where it will unveil the new Snapdragon 8 Gen 4 chip. MediaTek is expected to launch the Dimensity 9400 in mid-October.

Market estimates indicate that TSMC's 7nm, 5nm, and 3nm processes will continue to benefit from robust demand for notebook, smartphone, and AI chips. Alongside major customers like Apple, Intel, MediaTek, and Qualcomm, Nvidia's H100 and H200 chips, as well as the forthcoming Blackwell GPUs, are anticipated to make substantial contributions to TSMC's revenue.

Furthermore, with increased wafer starts from other major customers like AMD, Broadcom, Google, Microsoft, Meta, and Chinese domestic chip companies, TSMC is expected to easily surpass its third-quarter guidance of more than 11% sequential growth in US dollar revenue and a gross margin of 55.5%.

With TSMC's 3nm process operating at full capacity and the anticipated price increases for the 2nm process, set to enter mass production in the fourth quarter of 2025, the advanced process and CoWoS advanced packaging supply chain are expected to remain robust. Companies like Chusung, ASML, and Hongkang are anticipated to sustain strong business performance. TSMC's monthly capacity for the 3nm process is gradually rising from 100,000 wafers to approximately 125,000 wafers. Additionally, the 2nm fabs in Tainan Science Park and Kaohsiung are projected to achieve a monthly capacity of 120,000 to 130,000 wafers.