CONNECT WITH US

GUC announces tape-out of the world's first HBM4 IP on TSMC N3P

News highlights 0

GUC Announces Tape-Out of the World's First HBM4 IP on TSMC N3P. Credit: GUC

Global Unichip Corp. (GUC), the Advanced ASIC Leader, announced today that it has successfully taped out the world's first HBM4 controller and PHY IP. This test chip was implemented using TSMC's cutting-edge N3P process technology and CoWoS-R advanced packaging technology.

The HBM4 IP supports data rates of up to 12 Gbps under all operating conditions. By leveraging a proprietary interposer layout, GUC has optimized signal integrity (SI) and power integrity (PI) to achieve these high speeds for all types of CoWoS technology. Compared with HBM3, GUC's HBM4 PHY delivers 2.5x bandwidth while improving 1.5x power efficiency and 2x area efficiency. In line with previous GUC HBM, GLink, and UCIe IPs, this HBM4 IP integrates proteanTecs' interconnect monitoring solution to provide high visibility for testing and characterizing the PHY while improving in-field performance and reliability for end products.

This milestone further strengthens GUC's comprehensive portfolio of advanced IPs, including its 32Gbps UCIe-A and GLink-3D IPs. Together, these offerings deliver a complete 2.5D and 3D total solution, empowering customers to address the most demanding applications in AI, high-performance computing (HPC), and beyond.

"We are proud to be the first company to have taped out a 12Gbps HBM4 controller and PHY IP," said Sean Tai, President of GUC. "Our commitment to delivering best-in-class 2.5D/3D IPs and services remains strong. By integrating HBM4, UCIe-A, and GLink-3D IPs, we offer a comprehensive solution that meets the evolving needs of the semiconductor industry."

GUC HBM4 IP Highlight

• Signed off at 12 Gbps in full range of corners and operating conditions

• High bus utilization rate: ~90% at random read/write access

• Proprietary interposer layout to achieve best SI/PI for all types of CoWoS technology

• Embedded per-lane, in-mission mode I/O and Clock performance and health monitoring by proteanTecs

Article edited by Jack Wu