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Thursday 20 April 2017
ASML secures pull-in of EUV equipment orders
ASML has landed a pull-in of EUV lithography equipment orders with its backlog reaching 21 units, according to the company.
Wednesday 26 October 2016
Cadence IP tools certified on Samsung 10nm process technology
Cadence Design Systems has announced that its complete suite of digital and signoff tools has been certified for Samsung Electronics' Process Design Kit (PDK) and Foundation Library...
Monday 24 October 2016
Fujitsu adopts Cadence Palladium Z1 enterprise emulation platform
Cadence Design Systems, has announced that Fujitsu has adopted the Cadence Palladium Z1 enterprise emulation platform for the development of the ARMv8-based Post-K computer. The Post-K...
Monday 26 September 2016
Cadence, TSMC advance 7nm FinFET designs for mobile and HPC platforms
Cadence Design Systems has announced several important deliveries in its collaboration with TSMC to advance 7nm FinFET designs for mobile and high-performance computing (HPC) platf...
Friday 23 September 2016
Cadence delivers integrated system design solution for TSMC InFO packaging technology
Cadence Design Systems has announced the immediate availability of an integrated system design solution for TSMC's advanced wafer-level integrated fan-out (InFO) packaging technology,...
Wednesday 21 September 2016
Cadence delivers tools for implementation and signoff of new ARM Cortex-R52 CPU
Cadence Design Systems has announced the availability of a Cadence Rapid Adoption Kit (RAK) for the new ARM Cortex-R52 CPU, which targets complex embedded designs for safety applications...
Friday 15 July 2016
Micron intros SLC NAND flash for IoT and automotive
Micron Technology has announced its newest embedded SLC NAND flash optimized for the next generation of Internet of Things (IoT) and automotive applications. Available with differing...
Wednesday 13 July 2016
Intel certifies Cadence implementation and signoff tools for 10nm tri-gate process
Cadence Design Systems has announced that its implementation and signoff tools have been certified on the Intel third-generation 10nm tri-gate process for customers of Intel Custom...
Monday 30 May 2016
Cadence delivers rapid adoption kit based on 10nm reference flow for new ARM Cortex-A73 CPU and ARM Mali-G71 GPU
Cadence Design Systems has announced the availability of a Rapid Adoption Kit (RAK) based on the ARM internal flow used for the design of the ARM Cortex-A73 central processing unit...
Thursday 12 May 2016
Cypress adopts Cadence design tools for 40nm auto ICs
Cypress Semiconductor has selected the full Cadence RTL-to-signoff digital design flow and complete Spectre circuit simulation platform for all of its 40nm automotive chip designs,...
Tuesday 26 April 2016
Toshiba adopts Cadence Innovus implementation system for memory controller design
Toshiba has adopted the Cadence Innovus implementation system for its memory controller's production design project, according to the EDA company. The tool enabled Toshiba...
Thursday 14 April 2016
UMC qualifies Cadence Virtuoso LDE analyzer for its 28HPC process
Cadence Design Systems has announced that the company's Virtuoso layout-dependent effects (LDE) analyzer has been qualified by United Microelectronics (UMC) to support the foundry's...
Thursday 31 March 2016
Cadence digital and signoff tools certified on Samsung 14LPP process
Cadence Design Systems has announced that its complete suite of digital and signoff tools has achieved certification for Samsung Foundry's process design kit (PDK) and foundation...
Thursday 17 March 2016
Cadence design tools certified for TSMC 7nm design starts and 10nm production
Cadence Design Systems has announced that its digital, signoff and custom/analog tools have achieved V1.0 Design Rule Manual (DRM) and SPICE certification from TSMC for its 10nm FinFET...
Wednesday 16 March 2016
Cadence launches complete IC packaging design and analysis solutions for fan-out WLCSP
Cadence Design Systems has announced the availability of foundry-proven IC packaging design and analysis solutions for advanced fan-out wafer-level chip scale packaging (WLCSP) and...