Cadence Design Systems and United Microelectronics Corporation (UMC) have jointly announced that the US-based EDA firm's analog/mixed-signal (AMS) IC design flow has achieved certification...

Cadence Design Systems has announced that its digital full flow has achieved certification for the Samsung Foundry 5nm low-power early (5LPE) process with extreme ultraviolet (EUV)...

Samsung Electronics provided an update to its advanced-node process technology roadmap, including its 3nm gate-all-around (GAA) technology, during a recent company event in Santa...

TSMC has announced the expansion of its open innovation platform (OIP) cloud alliance, with Mentor Graphics joining inaugural members Amazon Web Services (AWS), Cadence, Microsoft...

TSMC has announced delivery of the complete version of its 5nm design infrastructure within the Open Innovation Platform (OIP). This full release enables 5nm systems-on-chip (SoC)...

The US-China trade war, a key threat to the global economy in 2018, will continue to play a pivotal role in 2019. But what does it mean to the world's biggest manufacturer and market,...

EDA vendor Cadence Design Systems is scheduled to start operating a new subsidiary in Nanjing, China in September, according to industry sources.

Cadence has disclosed a test chip containing next-generation DDR5 memory interface IP, which operates with Micron Technology's prototype DRAM chips. The test chip was fabricated in...

Cadence Design Systems has announced that Realtek Semiconductor used the Cadence Innovus implementation system for its 28nm Digital TV (DTV) system-on-chip (SoC) production tapeout...

Advanced Semiconductor Engineering (ASE) and Cadence Design Systems have collaborated to release a system-in-package (SiP) EDA solution that addresses the challenges of designing...

Cadence Design Systems has announced that HiSilicon, a global fabless semiconductor and IC design company, has selected the Cadence Tensilica Vision P6 DSP for its 10nm Kirin 970...

Xilinx, ARM, Cadence Design Systems and TSMC have announced a collaboration to build the first CCIX (cache coherent interconnect for accelerators) test chip in TSMC 7nm FinFET process...

ASML has landed a pull-in of EUV lithography equipment orders with its backlog reaching 21 units, according to the company.

Cadence Design Systems has announced that its complete suite of digital and signoff tools has been certified for Samsung Electronics' Process Design Kit (PDK) and Foundation Library...

Cadence Design Systems, has announced that Fujitsu has adopted the Cadence Palladium Z1 enterprise emulation platform for the development of the ARMv8-based Post-K computer. The Post-K...