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Thursday 14 April 2016
UMC qualifies Cadence Virtuoso LDE analyzer for its 28HPC process
Cadence Design Systems has announced that the company's Virtuoso layout-dependent effects (LDE) analyzer has been qualified by United Microelectronics (UMC) to support the foundry's...
Thursday 31 March 2016
Cadence digital and signoff tools certified on Samsung 14LPP process
Cadence Design Systems has announced that its complete suite of digital and signoff tools has achieved certification for Samsung Foundry's process design kit (PDK) and foundation...
Thursday 17 March 2016
Cadence design tools certified for TSMC 7nm design starts and 10nm production
Cadence Design Systems has announced that its digital, signoff and custom/analog tools have achieved V1.0 Design Rule Manual (DRM) and SPICE certification from TSMC for its 10nm FinFET...
Wednesday 16 March 2016
Cadence launches complete IC packaging design and analysis solutions for fan-out WLCSP
Cadence Design Systems has announced the availability of foundry-proven IC packaging design and analysis solutions for advanced fan-out wafer-level chip scale packaging (WLCSP) and...
Thursday 3 December 2015
Cadence unveils Virtuoso platform for 10nm processes
Cadence Design Systems has announced the delivery of the new Virtuoso advanced-node platform that is enabled for all 10nm FinFET designs. This next-generation custom design platform...
Tuesday 10 November 2015
Cadence announces tools enabled for Globalfoundries 22FDX platform
Cadence Design Systems has announced that its digital and signoff tools are now enabled for the current version of the Globalfoundries 22FDX platform reference flow. Globalfoundries...
Tuesday 13 October 2015
Cadence announces memory model for LPDDR5
Cadence Design Systems has announced the Cadence Memory Model for the LPDDR5 standard. This new verification IP (VIP) product enables engineers to verify that system-on-chip (SoC)...
Thursday 8 October 2015
Imec and Cadence complete tapeout of first 5nm test chip
Nano-electronics research center imec and Cadence Design Systems have announced that the companies completed the first tapeout of a 5nm test chip using extreme ultraviolet (EUV) as...
Wednesday 23 September 2015
Cadence offers design tools for TSMC InFO packaging
Cadence Design Systems has announced that its Allegro system-in-package (SiP) and physical verification system (PVS) implementation technologies have been enabled for TSMC's integrated...
Thursday 17 September 2015
Cadence announces IP portfolio for TSMC 10nm FinFET process
Cadence Design Systems has announced an intellectual property (IP) portfolio for TSMC's 10nm FinFET (N10) process. Cadence has already secured multiple design wins with this portfolio...
Tuesday 11 August 2015
Realtek accelerates SoC verification with Cadence Palladium XP platform
Cadence Design Systems has announced that Realtek Semiconductor utilized the Cadence Palladium XP platform to accelerate the development and verification of a recent system-on-chip...
Tuesday 9 June 2015
Cadence, TSMC collaborate on IoT IP subsystem
Cadence Design Systems has announced that it is collaborating with TSMC on the development of an Internet of Things (IoT) IP subsystem demonstration platform for TSMC's ultra-low...
Friday 5 June 2015
Cadence implementation and signoff tools certified on Intel 14nm Process
Cadence Design Systems has announced that its implementation and signoff tools have achieved certification on the Intel 14nm process for customers of Intel Custom Foundry. Intel Custom...
Wednesday 3 June 2015
Globalfoundries announces design infrastructure for 14nm FinFET process
In collaboration with design ecosystem partners, Globalfoundries has announced the availability of digital design flows for customers designing on its latest manufacturing technology...
Thursday 9 April 2015
Cadence digital and custom/analog tools achieve TSMC certification for 10nm FinFET early design starts
Cadence Design Systems has announced that its digital and custom/analog tools have achieved certification from TSMC for its most-current version of 10nm FinFET Design Rule Manual...