Intel targets entry-level advanced packaging, draws interest from Google and Amazon

Over the past decade, market assessments of Intel have largely been confined to a single lens: execution in advanced process technology. By that metric, Intel has struggled, with delays in 10nm and setbacks at the 7nm node, leading to the loss of Apple's chip orders. This view assumes that semiconductor manufacturing advantage is determined primarily by transistor density, particularly in the system-on-chip era.

But the defining question in 2026 is the shift from chip-level to system-level logic: who can integrate four, eight, or even up to 17 chiplets into a single package with near-zero performance loss to deliver a functional system?

Intel CFO David Zinsner said at the first quarter 2026 earnings call that he had previously estimated the advanced packaging business at only "a few hundred million US dollars," a supporting role compared with the foundry business, which could generate tens of billions in revenue. However, driven by AI ASIC demand, Intel has now raised its packaging outlook, with revenue potential expected to exceed US$1 billion.

More importantly, customers for EMIB and EMIB-T packaging are expected as early as the second half of 2026, bringing in several billion US dollars in revenue. While Intel has not disclosed its advanced packaging customers, foreign media have repeatedly named major players such as Google and Amazon as early adopters.

According to Yole, the advanced packaging market is entering a new phase of strategic growth, with a projected compound annual growth rate of 9.4% and a market size approaching US$80 billion by 2030.

As cloud service providers accelerate in-house ASIC development, demand for a larger packaging area to integrate more complex functions continues to rise. Some CSPs are considering shifting from TSMC's CoWoS solutions to Intel's EMIB technology. Nvidia is also reportedly evaluating EMIB for its next-generation Feynman product, potentially allocating up to 25% of packaging volume to Intel, with the remaining 75% staying with TSMC.

Setting aside advanced process competition, beyond Tesla CEO Elon Musk's public endorsement of Intel 14A, it remains unclear which customers may adopt Intel's nodes. What is evident is that Intel is quietly shifting strategy, targeting the entry-level segment of advanced packaging to win customers.

Sub-2nm race tough to reverse, packaging becomes Intel's entry point

A SemiVision report noted that the key development is not which process customers Intel secures, but its move to push advanced packaging to the forefront, potentially positioning it as the primary entry point for its foundry strategy.

By 2026, competition at sub-2nm nodes remains the hardest battleground to reverse, with limited chances of catching up to TSMC's process leadership in the near term. Advanced process competition is a long-term contest of trust. Customers care not only about theoretical node metrics, but also stable mass production, capacity expansion, yield consistency, on-time delivery, and the ability to sustain roadmaps across the next two to three product generations.

Advanced packaging offers a more pragmatic path aligned with AI-era demands. Using packaging as an entry point into hyperscale AI ASIC supply chains appears more realistic. Intel CEP Lip-Bu Tan is clearly leading this strategic shift.

If Intel can deliver advanced packaging, chip integration, and HBM-related capabilities through EMIB, Foveros, and EMIB-T to address system-level bottlenecks, adoption resistance could decline significantly. Partial integration lowers barriers compared with full platform replacement.

AI chips need more than process; packaging takes center stage

The bottleneck for AI chips today is no longer single-point compute performance, but system-level constraints. In the past, semiconductor competition centered on smaller transistors and higher density. That paradigm has changed.

Large language model training and inference require not only stronger compute chips, but also larger memory, faster interconnects, lower data transfer power consumption, and signal integrity and thermal stability across both the package and the overall system.

Packaging is no longer a backend support function. It has become a core component of system architecture. This is a reality that Nvidia, AMD, Google, AWS, and all ASIC teams must face. While companies can design their own computing chips, they cannot bypass packaging.

As AI ASIC customization deepens to meet specific workloads, customers increasingly need partners capable of delivering heterogeneous integration and advanced packaging at speed. This is one reason hyperscale data centers are placing growing importance on packaging suppliers.

Compiled by DIGITIMES, May 2026

Intel drops IDM rigidity, embraces hybrid packaging model

According to Intel, its foundry business is focused on promoting a portfolio of advanced packaging technologies, including Foveros 2.5D, Foveros Direct 3D, EMIB 3.5D, and EMIB-T, targeting large-scale AI and HPC applications.

The approach is clear: rather than integrating all functions into a single chip, Intel enables customers to flexibly combine different process nodes and functional modules through chiplet architectures, overcoming reticle limits while optimizing power consumption, bandwidth, and system flexibility. Intel also highlighted that EMIB and EMIB-T support larger package sizes and more flexible heterogeneous integration.

Wired previously cited a Fab 9 plant manager and a 31-year Intel veteran, who said one key selling point of Intel's advanced packaging is flexibility. Customers can choose to use Intel at any stage of the process, entering or exiting at different points.

For example, wafers can be produced at another foundry and then brought to Intel for packaging, or traditional packaging can be handled by OSAT providers before moving to Intel for advanced packaging. "This is not something Intel would have done before. This is a major shift in mindset."

Google, Amazon seen as key entry for Intel AI ASIC push

Google and Amazon are not traditional IC design firms but owners of AI infrastructure. Google develops TPUs, Amazon has Trainium and Inferentia, while Meta and Microsoft are also advancing in-house AI chip strategies.

They share a common approach: strong system-level understanding, data center control, and internal design capabilities, without necessarily committing capital to build full manufacturing and packaging ecosystems. Instead, they retain design control while outsourcing production and packaging to suitable partners.

As a result, they are not only seeking wafer suppliers but also system-level partners capable of delivering complete solutions. This represents a structural opportunity for Intel.

While reports of packaging orders from Google and Amazon remain unconfirmed, the direction is commercially logical and aligns closely with Zinsner's view of AI ASIC packaging opportunities.

Article translated by Levi Li and edited by Jack Wu