TSMC said its COUPE silicon photonics platform is set to enter volume production this year, as rising demand for high-speed interconnects in AI data centers pushes optical technologies closer to commercial deployment.
Speaking at a March 31 forum organized by SEMI's Silicon Photonics Industry Alliance (SiPhIA), the company said COUPE, short for Compact Universal Photonic Engine, would be a key step in bringing co-packaged optics (CPO) into data center systems.
Pressure builds for optical interconnects
The shift comes as generative AI and inference workloads place increasing strain on data center interconnects, exposing the bandwidth and power limits of conventional electrical signaling.
SEMI cited industry estimates showing silicon photonics modules are expected to account for more than half of the optical transceiver market by 2026, up from about one-third in 2024, reflecting a transition from research to broader deployment.
TSMC Vice President and SiPhIA co-chair Kuo-chin Hsu said the industry has moved closer to consensus over the past three to six months on technology roadmaps for the next three to five years, adding that SiPh has been elevated to a priority policy area.
COUPE moves from concept to manufacturing
Shang-yung Hou, director of advanced packaging integration at TSMC, said COUPE is no longer just a laboratory concept and has evolved into a semiconductor process technology designed for large-scale manufacturing. He said the platform is scheduled to enter volume production this year.
Hou said COUPE uses SoIC technology to heterogeneously stack electronic and photonic integrated circuits, shortening transmission distance and lowering power consumption.
He added that growth in advanced packaging such as CoWoS, driven by tighter integration of computing and memory, has led to larger interposer sizes. TSMC has taken a step-by-step approach to scaling interposers to balance performance gains against technical risk.
To address the energy and performance limits of electrical transmission, TSMC is introducing silicon photonics to replace part of the electrical interconnect with optical signaling. Hou said COUPE is designed to deliver high performance within a compact footprint and can support both waveguide couplers and edge couplers under a unified manufacturing architecture.
Testing and assembly remain key challenges
Hou said scaling CPO will require coordinated innovation across the supply chain, particularly in wafer-level testing, fiber array units, and high-speed optical packaging assembly.
He identified partners, including FOCI Fiber Optic Communications for fiber array unit assembly and testing, and MPI Corp. for optical test equipment, which are aimed at enabling automated wafer-level optical measurement and improving testing efficiency and precision.
TSMC said its roadmap includes multi-wavelength transmission technologies such as WDM and DWDM, with external laser sources expected to become a mainstream approach for CPO.
Credit: Samsung
Samsung outlines competing roadmap
Samsung Electronics has also formally entered the silicon photonics market, according to The Elec.
The company said at the Optical Fiber Communication Conference (OFC) 2026 that it had completed production readiness for its silicon photonics foundry platform, including development of a process design kit, and plans to manufacture the technology using 300mm wafers.
According to the report, Samsung plans to start with photonic ICs, introduce optical engines in 2027, apply hybrid copper bonding in 2028, and launch turnkey CPO services in 2029. Its modulator technology has reached data transmission speeds of 224Gbps per lane, based on measurements conducted by imec.
Samsung said its vertically integrated model, combining memory, foundry, packaging, and SiPh, differentiates it from TSMC, which does not produce memory.
Article edited by Jack Wu
